Attached is my Picasso drawing of the MOS circuit I want to be able to understand the answer for the truth table of this circuit.

The N-substrate also goes to 0V

The truth table is as follows:

Va Vb Vo
0V 0V +5V
0V +5V 0V
+5V 0V +5V
+5V +5V 5V



More specifically, I do not understand when the first N-gate to the right is getting 5V or 0V, due to the input of the connecting being some kind of function of the voltage just below the resistor. Thankyou!

 

woops, the circuit attached is a TTL circuit, I have converted the question from a mos to TTL and am happy to draw the MOS configuration if necessary!

 

The second dual gate conducts only if botth inputs are +. This happeens when a is 0, B is plus. the output V0 is then 0.

 

Would you be able to explain to me what happens at each instance? For example...i picture that when vA=0V and vB=0V, the gate on the left stays open and the bottom right gate is also open..Im not sure how the top right gate is affected in all input cases..

 

I redrawn your diagram.
And lets try analysis the circuit for
VA = 0V and VB = 0 V.
Since VA is equal 0V so T1 is OFF and T3 is also off.
T2 will be "ON" but there is no path to GND for T2 current to flow (because T3 is "OFF").
So Vo = Vdd = 5V

 

Ahh thankyou. Would you also be able to explain the last three combinations...more in particular when vA = 5V and vB =0V and also when Va=5v and vb = 5v?...I am still struggling with these two situations.

 

Well i give you a hint.
When MOSFET's are "ON" treat them as short circuit.
And when MOS are "OFF" treat them as a open circuit.

 

oh I see! Thankyou very much!!