monte carlo simulation

Discussion in 'Analog & Mixed-Signal Design' started by kevin.1, Oct 14, 2016.

  1. kevin.1

    Thread Starter New Member

    Dec 2, 2014
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    I have designed too many op amps and none of them have any issue with a wide range variations of supply voltage , temperature , corners of process , worst case pvt circumstances , etc . but the problem is the monte carlo analysis by which my op amps are all totally devastated .I know the monte carlo analysis has quite a different scenario from the abovementioned ones and it contains the random mismatches but I tried so many bias circuits with different levels of bias voltages and different schems for sizing the transistors in both 0.35um and 0.18um and mostly for folded-cascode and telescopic topologies and I mostly use the bias circuit presented in gray (p. 847) for folded-cascode , as I already mentioned I used other circuits as well , but mostly that one in the gray . but the results of just monte carlo are terrible(I really do mean it) in either technologies and any bias strategies or any topologies ( either traditional op amps or proposed ones) and any overdrive levels and any sizing regimes (specially large sizes to reduce the random mismatch effects but neither small nor large size did work )and it is really busting and I do not know what the solution to this problem is . I already googled over and over to find a solution to cope with it there was some literature which said to set the overdrive voltages of diff pairs low and the current mirrors high to lower the mismatches and I did so but it did make no difference whatsoever . here is the way by which I perform monte carlo analysis for threshold voltage mismatches(a traditional way which is used mostly in monte carlo analysis) I put a voltage source in series with the gate of all paired transistors but with opposite polarity in each and for example I write the following commands in hspice for an NMOS transistor with w=100um , l=0.18um , m=1.

    m1 3 vin+ 1 0 nch l=.18u w=100u m=1
    vmcin+ vin+ vinp dvthin+
    .param dvthin+ =agauss(0,0.001,1) ( according to the formula (5e-9(v)/sqrt (w*l*m))

    is that right? because I have seen way more larger values for that ( for example 0.01 with which my op amps are all completely bled white.)please somebody tells me if the problem stems from the biasing technique or sizing strategy or the way by which I do the simulation or any other cases .
     
  2. wayneh

    Expert

    Sep 9, 2010
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    I won't pretend to follow all that, but can you plot the voltages that are produced by your MC simulation? Maybe it's not doing what expect. You want a normal distribution centered on the mean voltage.
     
  3. kevin.1

    Thread Starter New Member

    Dec 2, 2014
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    what do you mean by voltages produced by MC simulation ? you mean the operating point of transistors or nodes dc voltages or the voltage sources which have been inserted between the gates and dc biases? would you please make yourself clear?
     
  4. wayneh

    Expert

    Sep 9, 2010
    12,118
    3,042
    What I meant it to examine the outputs of any MC simulation, before it is applied to your circuit, to see if the algorithm is producing the mean and standard deviation you would expect for the variables of interest. I assumed the result was a voltage but really it's a bell curve with a mean and a standard deviation. Ever variable is assumed to be drawn from a population with a degree of random diversion around the central mean. So every variable, when sampled many times, should show you that bell curve.

    My suggestion is to eyeball those bell curves to see if they make sense to you.
     
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