Hi all,

I feel very confused with the oppsitition between the explaination in text and the diagram which is illustrated.
The explaination in text:
"When a positive trigger pulse is applied to the input at time t0, the output of the first NOR gate U1 goes LOW taking with it the left hand plate of capacitor CT thereby discharging the capacitor. As both plates of the capacitor are now at logic level "0", so too is the input to the second NOR gate, U2 resulting in an output equal to logic level "1". This then represents the circuits second state, the "Unstable State" with an output voltage equal to +Vcc"

But in the diagram, the capacitor is charging.
As for me, I think that positive trigger pulse is applied to the input at time t0 the capacitor is charged because the output of NOR gate U1 is low and the right plate of cap is High.
But I dont see how cap is discharged because when output of NOR gate U1 is High and the right plate of cap is High, hence there is no voltage dropping in capacitor and cap is not discharged.
Am I right?
Thanks so much.

 

Remember that a gate output is a switch, it goes low and high, so provides a current path depending on what state it is in. If it is high, it is indirectly connected to Vcc, if it is low it is connected to ground.

 

Remember that a gate output is a switch, it goes low and high, so provides a current path depending on what state it is in. If it is high, it is indirectly connected to Vcc, if it is low it is connected to ground.

Thanks.
Sorry but I am not really understand what you say?
In this circuit the gate is NOR and output state of its is depended on two input pins.
Could you give me more detailed explaination about this?

 

Hello,

Have a look at this page from the eBook:
TTL NOR and OR gates

Bertus

 

Hello,

Have a look at this page from the eBook:
TTL NOR and OR gates

Bertus

Thanks.
I think I have a good knowledge about logic gates.The problem is that how the capacitor in the above circuit is discharged.

 

Before the trigger input we have this situation


And when a positive trigger pulse is applied to the input at time t0, the output of the first NOR gate goes LOW. And this starts the process of charging the capacitor

When the voltage across the capacitor reach gate two threshold voltage (0.5Vdd).
The U2 gate change his output stage from high to low. And this will cause the first gate to switch his output from low to high.

And the capacitor start to discharge through resistor R and P channel MOS built-in in the first gate.

 

Let me give my problem in detail.
When t<to both two inputs of NOR gate U1 is low level, therefore output of this NOR is high level and Um = Vcc because N is connected to Vcc => Un=Vcc
then Uc= 0 V.
At the time t= to, input pulse goes high => output of U1 is low and capacitor is charged and Un= 0V => output of U3 is high
Could you help me explain why Uc=0 like above explaination.

 

I would like to add that in real life the voltage at the U2 gate input don't reach 7.5V.

This is because all CMOS gates has a input diode protection circuit. And this protection circuit reduce the gate input voltage to about 5.7V. And there will be additional discharge current flow through input protection diode.
This input protection diode is connect parallel to RT resistor

 

Thanks you so much for your usefull and clearly explaination.
It is very clearly and I really appreciate it.
Could you help me explain why when a positive trigger pulse is applied to the input at time t0, both plates of the capacitor are now at logic level "0"?
I thought it is high level because it is connected to Vcc.

 

Thanks you so much for your usefull and clearly explaination.
It is very clearly and I really appreciate it.
Could you help me explain why when a positive trigger pulse is applied to the input at time t0, both plates of the capacitor are now at logic level "0"?
I thought it is high level because it is connected to Vcc.

Thanks all help.
Now i understand, I feel so shy for this quesions.
Thank again.

 

Thanks all help.
Now i understand, I feel so shy for this quesions.
Thank again.

Don't feel shy.
You know the answer already.
But the answer is simply: the capacitor is empty so he act just like a short circuit.

 

I would like to add that in real life the voltage at the U2 gate input don't reach 7.5V.

This is because all CMOS gates has a input diode protection circuit. And this protection circuit reduce the gate input voltage to about 5.7V. And there will be additional discharge current flow through input protection diode.
This input protection diode is connect parallel to RT resistor

The original circuit uses a 74LS02, which is TTL. The diode from input to Vcc is still there, but it doesn't have any current-limiting resistor, AFAIK. Fortunately, the sourcing current on 74LS is pretty low, so the diode should be OK.