Modulo 8 down counter using Altera Quartus II 9.2 SP

Discussion in 'Homework Help' started by Jan C, Dec 3, 2014.

  1. Jan C

    Thread Starter New Member

    Dec 3, 2014
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    i need to design a modulo 8 down counter using Altera Quartus II 9.2 SP and my professor gave us a hint to use 74192 or 74193 chip in the program with parallel load. the counter has to count from 8 to 1 and the output all the outputs seems to stay low. Can someone please help me?
     
  2. WBahn

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    Mar 31, 2012
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    Is the problem with designing the logic or with using Quartus?

    What does your design look like?

    Typically a modulo-8 counter would count 7,6,5,...,1,0,7,6,.... Are you sure you are supposed to add 1 to all of these? If so, how are you doing that (which gets back to what does your design look like)?
     
  3. JoeJester

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    Apr 26, 2005
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    According to https://www.altera.com/download/sw/dnl-sw-index.jsp

    there is no Altera Quartus II 9.2 SP

    Which service pack of version 9.1 did your instructor tell you to use?

    By the simulation software I'll assume your using a FPGA and interfacing to the 74192 or 74193.

    Did you program the FPGA?

    You should be able to do a screen shot and paste it into paint, then crop it, and post it here for the members to see what you have done.
     
  4. WBahn

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    Mar 31, 2012
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    I'm reading between the lines here, but I was imagining that the '192 and '193 are parts in the library that can be used as part of a design that is then implemented within the FPGA. I would imagine that this would make sense and be desirable from the standpoint that someone that is familiar with doing designs using standard family devices can keep doing that and then just target an FPGA at the end of the day. It probably also makes it easier to port existing designs to an FPGA implementation.

    But I definitely agree that a screen shot and more thorough description would be helpful.
     
  5. JoeJester

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    I agree WBahn. I'll wait for some feedback from the OP for now.
     
  6. Jan C

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    Dec 3, 2014
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    Sorry I made an error its Altera Quartus II 9.1 SP 2

    I attached a block diagram of the chip. My professor mentioned some important things which were:
    1. The MSB for a particular counter is D
    2. LD and CLR are both asynchronous
    3. whichever clock is not being used it must be tied to high

    I'm not sure what CON and BON is because he never introduced us to the chip. Would you guys want to see the logic inside the chip or is it not necessary?
     
  7. djsfantasi

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    Apr 11, 2010
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    I am assuming by "the chip" you are referring to the 74192 or 74193. You should be able simply download the datasheet for these chips and answer your own questions. For example, here is a link to the datasheet.

    The pin out is shown below. Note there are two pins which are the only logical candidates for CON and BON. Also note they are active low, meaning that when they are true, they will be low.
    [​IMG]
     
  8. Jan C

    Thread Starter New Member

    Dec 3, 2014
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    I don't understand how my simulation is always outputing 0 though even though I need to be able to create a down counter from 8 to 1.
    and the pin out is not necessary as I am running this on Altera Quartus II
     
  9. djsfantasi

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    Apr 11, 2010
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    I supplied the pin out and datasheet because of what you said.
    Hopefully, from the datasheet you can determine what CON and BON are and what they do. One of them may help your simulation.
     
  10. JoeJester

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    Apr 26, 2005
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    Can you do a screen shot of your work in the simulation software?

    Posting a single chip, and asking why your outputs are staying low only has us waiting on more information.
     
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