Modelling a serial transmission system in VHDL

Discussion in 'Programmer's Corner' started by andy24691, May 22, 2011.

  1. andy24691

    Thread Starter Member

    Nov 25, 2010
    42
    0
    I have to design and build a system capable of the following;

    1) A 4-bit number is to be obtained from a 4-bit dil switch and on the press of another switch the 7-bit ASCII equivalent is to be transmitted via a simple synchronous serial comm link.
    2) The comm link is to operate on ttl levels and comprises three wires: data, ground and clock.
    3) A receiever is to detect when a transmission has ocured and display the hexidecimal equivalent on two 7-seg displays.

    The code below is for the transmitter, I'm not very knowledgable when it comes to VHDL so I apologise if its filled with 'obvious' errors. To the best of my limited ability I have attempted to debug the programme but it refuses to compile. Could anyone be able to help me out? Please reply in the simplest possible terms.

    Cheers

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity transmitter is port(
    bin: in unsigned (3 downto 0);
    sout: out std_logic;
    shift, load, clk: in std_logic);
    end transmitter;

    architecture module1 of transmitter is
    begin
    process(bin, shift, load,clk)
    variable temp: unsigned (6 downto 0);
    variable index: integer;
    begin
    if load ='1' then
    case bin is
    when "0000" => temp:= "0011110";
    when "0001" => temp:= "0011111";
    when "0010" => temp:= "0100000";
    when "0011" => temp:= "0100001";
    when "0100" => temp:= "0100010";
    when "0101" => temp:= "0100011";
    when "0110" => temp:= "0100100";
    when "0111" => temp:= "0100101";
    when "1000" => temp:= "0100110";
    when "1001" => temp:= "0100111";
    when "1010" => temp:= "0101001";
    when "1011" => temp:= "0101010";
    when "1100" => temp:= "0101011";
    when "1101" => temp:= "0101100";
    when "1110" => temp:= "0101101";
    when "1111" => temp:= "0101110";
    end case;
    end if;
    if shift = '1' then
    index := 0;
    else if shift = '0' then
    index := 7;
    end if;

    while index < 7 loop
    if rising_edge(clk) then
    temp:= temp ror 1;
    sout <= temp(6);
    index := index + 1;
    end if;
    end loop;
    end if;
    end process;
    end module1;
     
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