I have to design and build a system capable of the following;

1) A 4-bit number is to be obtained from a 4-bit dil switch and on the press of another switch the 7-bit ASCII equivalent is to be transmitted via a simple synchronous serial comm link.
2) The comm link is to operate on ttl levels and comprises three wires: data, ground and clock.
3) A receiever is to detect when a transmission has ocured and display the hexidecimal equivalent on two 7-seg displays.

The code below is for the transmitter, I'm not very knowledgable when it comes to VHDL so I apologise if its filled with 'obvious' errors. To the best of my limited ability I have attempted to debug the programme but it refuses to compile. Could anyone be able to help me out? Please reply in the simplest possible terms.

Cheers

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity transmitter is port(
bin: in unsigned (3 downto 0);
sout: out std_logic;
shift, load, clk: in std_logic);
end transmitter;

architecture module1 of transmitter is
begin
process(bin, shift, load,clk)
variable temp: unsigned (6 downto 0);
variable index: integer;
begin
if load ='1' then
case bin is
when "0000" => temp:= "0011110";
when "0001" => temp:= "0011111";
when "0010" => temp:= "0100000";
when "0011" => temp:= "0100001";
when "0100" => temp:= "0100010";
when "0101" => temp:= "0100011";
when "0110" => temp:= "0100100";
when "0111" => temp:= "0100101";
when "1000" => temp:= "0100110";
when "1001" => temp:= "0100111";
when "1010" => temp:= "0101001";
when "1011" => temp:= "0101010";
when "1100" => temp:= "0101011";
when "1101" => temp:= "0101100";
when "1110" => temp:= "0101101";
when "1111" => temp:= "0101110";
end case;
end if;
if shift = '1' then
index := 0;
else if shift = '0' then
index := 7;
end if;

while index < 7 loop
if rising_edge(clk) then
temp:= temp ror 1;
sout <= temp(6);
index := index + 1;
end if;
end loop;
end if;
end process;
end module1;

 

Hi andy, your code managed to make quartus crash!

after removing the loop, i am told that temp doesn't hold its value outside a clock edge. this means that somebody could change the "bin" switch, inbetween a clock pulse, and that means that a register which holds the value temp cant be clocked.thats kind of a problem, as all the registers in a PLD or FPGA are generally clocked. it would be safe to make temp only change on a clock edge.

secondly, there is a command ElsIf, which is different from Else If. the second is a nested if statement, which i don't think you meant.

if shift = '1' then
             index := 0;
else 
             if shift = '0' then
                            index := 7; 
             end if;

            while index < 7 loop

                     if rising_edge(clk) then
                                 temp:= temp ror 1;
                                 sout <= temp(6);
                                 index := index + 1;
                    end if;

            end loop;


end if;

that indentation should help you understand how the compiler is interpreting your code.

the next thing to point out is that integers can be declared with a range. for a small chip, such as the palce 16v8 this may be a problem, so give it a range to limit it to only the required number of bits.

finally, i don't think my software likes your loop statement. maybe yours doesn't either. this code is writable without looping anything, and unclocked loops really don't make sense to me in logic design.

also,i bet you get asked to use the code tags around stuff.