I was wondering to built a mod 13 asynchronous counter using D flip flop, do I use D as outputs from the Q(t+1) or the compliments of Q(t+1) and do I also include the unused states as well? ex: present state: WXYZ--> present state: 0110--> next state: 0111. The input of D flip flop of Z=1?? or D-FF of Z =0?? (I think I have to derive the formula of SOP for the 4 D-FF by using the k-map, let me know if this is right)
To construct a 4 stage async. counter, need to pick D FF with independent clock input, such as 4013, a dual FF. Obtain a data sheet with pin out & truth table. The D is an input, if H is transferred to Q on next + clock.as a H; therefore if the not Q is connected to D that FF will act as a toggle FF. Connect 4 stages & then connect Q to suceeding stage Clock input for the last three stages.You now have a 0-15 counter. For divide by 13, subtract highest order bit,8= 5 5-4=1 we have 8,4, 1 to connect to a 3 in AND gate. Count 13 & 15 , both give an output of 13, but 13 is reacher first so not2 is not neered this time. Draw it up if you would like it checked.