MINMAX block of MATLAB VERILOG Code

Discussion in 'Programmer's Corner' started by sarathisme, Jul 8, 2016.

  1. sarathisme

    Thread Starter New Member

    Jul 8, 2016
    1
    0
    Hi ,
    I am doing a project on SVPWM for three level inverter using FPGA. 90 percentage of the program has been coded and now I am facing a problem with generating the control signals using MINMAX block of MATLAB. Can you help me to code the block in Verilog?
    The input to the block is three phase sine wave .
    Hope you have understood.
    Please help me ...
    The screen shot of the complete block is attached . Please someone help me to implement it in VERILOG
     
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