Hi, perhaps someone can help straighten out my confusion.

I have some 74HC14N Schmitt-Trigger inverters from TI,
(http://www.ti.com/lit/ds/symlink/sn74hc14.pdf) with my Vcc about 4.5v.

On a breadboard I drive the first inverter with a slow voltage from a potentiometer that
I manually adjust. (25K, outer legs tied to Vcc and Ground, middle point to the input of the
first trigger inverter.) The first inverter output feeds the second inverter input.

The circuit works as expected with a hysteresis gap between ascending and descending trigger levels,
provided I transition the input fast. But if I allow the input voltage to linger in "no-man's-land",
between the two trigger levels, I see the output of both inverters sit somewhere near Vcc/2, with a
fast oscillation (about 100 Mhz, maybe 0.7v p-p), on both the outputs of the first and second gate.

I found something that further deepened my confusion:
http://www.nutsvolts.com/magazine/a...ners-guide-to-reliable-timers-and-oscillators
<quote>
1) The logic gate has no well-defined input thresholds. Near an input voltage of approximately Vcc/2,
this alleged digital device behaves as a high-gain linear amplifier. Normally, this input region is
transitioned very rapidly in pure interconnected logic and is not a problem,
but when passive components are added as loads, this may not be the case.

2) Since passing through the input “no man’s land” near Vcc/2 must be done rapidly,
each CMOS logic family has a minimum input slew rate requirement. For example,
the 74HC family specifies a fast rise time of at least 11 volts/microsecond...
</unquote>

My confused expectations are
a) that the trigger-inverter output should latch close to Vcc or ground with
some kind of reinforcing feedback, without any possibility of outputs lingering elsewhere.
b) that slow signals and slew rates ought to be fine with a Schmitt trigger, e.g. if
I wanted to use this device connected to a temperature sensor, I thought it should work.

Any suggested reading or advice to help me understand what is going on? Obviously the fact
that I'm breadboarding a high speed CMOS device with little concern for layout and stray
capacitances might be a problem. I did tie unused gate inputs down and I did put a
capacitor across Vcc, just in case ...

Thanks
Peter

 

What are your two measured transition levels?

ak

 

Try it with the second inverter gate disconnected.
You may be getting feedback from the second gate's output to the first gate's input.

 

Like any typical transistor switch it has a linear region. In that linear region it has high gain and will operate as a class A linear amplifier. This is one reason why designers of CMOS digital logic circuits are advised to make sure that all unused inputs are tied to a defined logic level. There is nothing magical going on here. In saturation and cutoff a high gain amplifier makes a pretty good logic device. In the linear region in between saturation and cutoff -- not so much. AFAIK there is no latching action going on. The output level depends on the inputs unless they hang around in the threshold regions.

 

Like any typical transistor switch it has a linear region.

That's true for standard gates but it should not be true for Schmitt-trigger gates.
They have hysteresis on the input switching levels to avoid the oscillations that a linear region could generate.

 

So the inverter has about 100 MHz on its output,
The output is reacting with the input,

The HC14 has only around 200 mV hysteresis,
and that is assuming the power supply does not 'wobble',

The HC14 is to a first level approximation, a high speed / high gain inverting amplifier.

so what you have as you guessed, is an oscillator,
when the input is near Vcc or Gnd, then the output has little effect on the input .

decoupling of power supplies, de glitching the input with decoupling will all help

if you have one of those bread boards with long strips, then they are terrible at high speed stuff, you need to be very careful with decoupling

 

Try it with the second inverter gate disconnected.
You may be getting feedback from the second gate's output to the first gate's input.

That would be in phase with 2 inverters in series - it would enhance the Schmitt action.

In fact a feedback resistor of a few M is often strapped over a pair of inverters for that purpose.

 

At 100 MHz, one cycle is 10 ns. That means the propogation delay through each gate is significant fraction of one cycle, or a large phase shift. Large enough to make standard assumptions about one inverting injecting 180 degrees of phase shift not apply to this situation. The H in HC stands for high speed, but that actually is *relatively* high speed compared to a standard 4000 series gate, which is not all that fast.

ak

 

It is possible that you are getting feedback with a 25kΩ pot.
Try it with 1kΩ pot.

Or adding 10pF on the input to ground should kill the oscillation.

What is your circuit application?
Maybe you really need an analog comparator and not a Schmitt Trigger.

 

At 100 MHz, one cycle is 10 ns. That means the propogation delay through each gate is significant fraction of one cycle, or a large phase shift. Large enough to make standard assumptions about one inverting injecting 180 degrees of phase shift not apply to this situation. The H in HC stands for high speed, but that actually is *relatively* high speed compared to a standard 4000 series gate, which is not all that fast.

ak

The TS said; "a slow voltage from a potentiometer". The only mention I could find of 100MHz seems to refer to an unwanted parasitic oscillation - that would probably disappear if you reinforce the switching thresholds by enhancing the Schmitt action with a bit of pfb across 2 inverters in series.

 

that would probably disappear if you reinforce the switching thresholds by enhancing the Schmitt action with a bit of pfb across 2 inverters in series.

But not if there's a 180 degree phase shift through the two inverters at high frequency, hence the high frequency oscillation.

 

But not if there's a 180 degree phase shift through the two inverters at high frequency, hence the high frequency oscillation.

If the TS was running the circuit at 100MHz, that could be a problem - but its being operated slowly by a potentiometer as the TS stated.

The 100MHz parasitic oscillation is a symptom - not the cause.

 

If the TS was running the circuit at 100MHz, that could be a problem - but its being operated slowly by a potentiometer as the TS stated.

The 100MHz parasitic oscillation is a symptom - not the cause.

Yes it's a symptom of parasitic feedback.
This causes the observed oscillation at the frequency where the phase-shift through the two inverters is 180 degrees total.

 

Yes it's a symptom of parasitic feedback.
This causes the observed oscillation at the frequency where the phase-shift through the two inverters is 180 degrees total.

Indeed - but if you sharpen the Schmitt thresholds; it'll snap out of it.

Mucking about with phase angles is a good way to run yourself ragged..................

If a bit of pfb didn't fix it; I'd try about 22 - 33R in series with the load, excessive load capacitance could be causing instability in the totem pole output. It would also help damp ringing if there's a long inductive trace.

 

Indeed - but if you sharpen the Schmitt thresholds; it'll snap out of it.

But that won't necessarily work with capacitive feedback around the two inverters, since that could just enforce the feedback path causing the oscillation.

 

My point was that depending on the propagation delay through two inverters, two inverters in series with some form of coupling from the output back to the input might be guaranteed *not* to oscillate at some high frequency.

Or, the DC bias (at a high equivalent impedance) could be centering the input to receive a local FM station. Back in the 70's when WOSU-TV moved their transmitter from the edge of campus to outside a suburb, an OSU physics ultra-low temperature lab was able to start doing some experiments during the day.

ak

 

But that won't necessarily work with capacitive feedback around the two inverters, since that could just enforce the feedback path causing the oscillation.

If you mean parasitic capacitance - how the hell have thousands of people successfully used Schmitt trigger gates over the past 40 or so years?!!!.

 

If you mean parasitic capacitance - how the hell have thousands of people successfully used Schmitt trigger gates over the past 40 or so years?!!!.

Of course they work under most conditions, in hell or out.
I thought we were talking about this particular instance where the op was having an oscillation problem.

 

Thanks for the discussion! I'm a hobbyist, so there is no specific application, circuit, or agenda. (Not even homework

Ian's suggestion of some feedback eliminated the apparent "no-mand's land" issue and killed the oscillation. With a 2.2M meg feedback resistor (either negative feedback from the output of the first inverter, or positive feedback from the output of the second inverter), edges are crisp, oscillation disappears, and I cannot reproduce my original issue. Trigger levels are about 1.9v and 2.4v, and this looks consistent with the datasheet.

But what I did find (without that feedback resistor) is that the "problem region" I have only occurs on a falling input: when the input falls below 1.9v, the output jumps into the mid-range oscillation. The problem region is about 0.4v of input, so once input falls below 1.5v the output jumps unambiguously high. When my input voltage is climbing, the transition is always crisp.

It appears that this device separates the notion of hysteresis from the notion of latching the rising output. Without external feedback it tends to act like PapaBravo and AndrewMM suggested - a device with a (smallish) linear region between saturation and cut-off.