Memory Mapped vs I/O Mapped Input Output

Discussion in 'Computing and Networks' started by spartai, Dec 4, 2014.

  1. spartai

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    Dec 4, 2014
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    I'm currently reading a computer organization book and i'm so confused about Input/Output mechanism and have lots of questions in my mind.

    As i understood there are two concepts for communicating with peripherals, first one is Memory Mapped I/O and the other one is I/O(Port) Mapped I/O.If the architecture is based on Memory Mapped I/O there are no special I/O instructions like "in","out" etc and device registers are mapped to memory address space so we can read or write to peripheral ports by "mov" instruction.On the other hand if architecture is based on I/O Mapped I/O, device registers are mapped to I/O address space which is completely separated from memory address space and cpu uses special instructions("in","out","ins","outs" ) for reading or writing to I/O Mapped device registers.

    So here is my questions;

    1.)If X86 architecture uses I/O(Port,Isolated etc) Mapped I/O technique why there are memory address spaces for devices like graphic card?

    2.)If graphic card maps 1 gb memory to main memory address space what does it mean?Does it mean Memory Mapped I/O ?

    3.)If x86 architecture doesn't use Memory Mapped I/O how a device can maps itself to memory address space?

    4.)If x86 architecture can use Memory Mapped I/O ,how can it use and with which instructions?

    5.)If I/O mapping is about mapping peripheral registers why graphic card wants so much space for mapping ?
     
  2. Papabravo

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    1.)If X86 architecture uses I/O(Port,Isolated etc) Mapped I/O technique why there are memory address spaces for devices like graphic card?
    You can use memory mapped I/O in any architecture by replacing memory at a given range of addresses with I/O registers. Nothing in the architecture prevents you from doing this.
    2.)If graphic card maps 1 gb memory to main memory address space what does it mean?Does it mean Memory Mapped I/O ?
    It means that the graphics card is supplying a resource at those addresses, that is not provided by the system motherboard. You can't have two entities trying to supply memory or anything else at the same address.
    3.)If x86 architecture doesn't use Memory Mapped I/O how a device can maps itself to memory address space?
    A device will decode the address lines and the control signals from the processor and it must decide if it exists in the I/O space or the memory space. Usually there will be a conventional agrrement on what various segments of the address space can be used for. The original PC had an upper memory limit of 640K (who would ever need more?) because higer addresses were used for video information.
    4.)If x86 architecture can use Memory Mapped I/O ,how can it use and with which instructions?
    Any x86 instruction that writes a value to an address can be used.
    5.)If I/O mapping is about mapping peripheral registers why graphic card wants so much space for mapping ?
    Not sure I understand the first part of your question. A graphics card needs a great deal of space because each pixel requires several bytes worth of information. Quick how many pixels are there on a 1920 x 108 monitor?
    Answer: 2,073,600
     
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  3. spartai

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    Dec 4, 2014
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    "You can use memory mapped I/O in any architecture by replacing memory at a given range of addresses with I/O registers. Nothing in the architecture prevents you from doing this."

    But how? How is it possible in X86 architecture, the books that i've read says that "mov" instruction is used for communication between memory and cpu registers and "in,out" instructions are used for communication between cpu and device registers(control,status,data) so let's think a graphics card is mapped to memory with address range 0x000A0000 - 0x000BFFFF, if i send data to 0x000AAAAA address with "mov" instruction will it goes to main memory or device itself?
     
  4. Papabravo

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    A mov instuction activates different control signals than the {in,out} instructions. {in,out} instructions have an address space of 64K in the range [0x0000 - 0xFFFF]. The mov instruction has a much larger space. The answer to your other question is that you have to know where "main" memory begins and ends. IIRC addresses in the range [0xA0000 - 0xBFFFF] are physically on the graphics card and not in main memory. What is physically implemented at these addresses could be IO registers or memory or a mixture of the two. Access to IO registers in this address range is only possible with a mov instruction. It is also possible to allow the {in,out} instructions to access these registers by mapping the memory addresses into the IO space.

    On the schematic you should look for a signal called IO/M. This tells you that the address is an IO address triggered by {in,out} or a memory address triggered by mov.
     
    Last edited: Dec 5, 2014
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  5. spartai

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    Why I/O space is so small? If we use the address range [0xA0000 - 0xBFFFF] for graphics card isn't it a waste of main memory space? I mean if we use "mov" instruction with these address range, data is directly going to graphics card memory right? Isn't it a bad architecture? There is a completely useless address space in main memory?
     
  6. takao21203

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    In 1979 they had 300 baud modems and by todays money they costed $2000. What do you expect?
     
  7. Papabravo

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    You won't get any argument from me that the x86 is a bad architecture. Who cares what I think, the guys at Intel got rich with a bad architecture, and I'm a retired senior citizen on a fixed income. Go figure!
     
  8. MrChips

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    I care. I had a lot to say against the Intel/IBM/MS design. That computer kludge set back computer development and advancement a number of years in my books.
     
  9. Papabravo

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    Geez! Here I thought I was all alone.
     
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  10. shteii01

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    Progress.
    In 1970s it was large. In 2014 it is small. Progress.
     
  11. spartai

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    haha :)), but really the main issue is not x86, other architectures doesn't use I/O space anyway, i really can't understand this concept; why do we waste physical main memory for peripherals? If I/O mapped I/O doesn't waste any main memory space why all architectures do not use this concept and make the I/O space bigger? On the other hand does DMA use this address range for direct accessing to peripheral?
     
  12. Papabravo

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    The peripherals have to go somewhere. Having a large linear address space, like the Motorola MC68000, has some advantages. I first encountered this concept in the PDP-11 Unibus architecture. Its companion the PDP-8 had a separate IO space just like the x86.

    DMA controllers can access both main memory space and I/O space for either side of a transfer. The difference is that main memory accesses increment the address register and peripheral space accesses leave the address register unchanged
     
  13. nsaspook

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    The modern x86 has an MMU/Virtual machine/Virtual memory so you don't really waste physical memory space in a user-land program because you can have a unified address space of many physical bus spaces. If you had built a computer from the 8080 series then you would understand why the legacy I/O port kludge is still in the x86 series to make it compatible but it's almost never used today with a modern OS. About the only place these direct I/O space issues are relevant is in the BIOS code before the MMU is programmed. The truth is the X86 as hardware doesn't exist in modern CPU devices. It's emulated on a completely different core that just looks like a X86 until you get to the internal microcode cache.
     
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  14. Papabravo

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    Try talking to an emulated serial port on a PC and you'll understand what the phrase "drinking from a fire hose" is all about. A file transfer to a serial port is done in one DMA operation at the syncronous limit. You can't keep up cuz the PC will beat you with virtual memory every time. You can't even do XON/XOFF any more because once the DMA starts you can't interrupt it.
     
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  15. spartai

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    It's a good answer thank u, finally where the MMU belongs to? Is it inside the cpu or northbridge ? And how the MMU is programmed with assembly instructions?
     
  16. nsaspook

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    I think most have been integrated into the CPU now but in older Pentiums it was in the chipset..
    This is the boot sequence of a modern x86/x64 architecture PC.
    http://resources.infosecinstitute.c...x86x64-architecture-part-1-pci-based-systems/
     
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  17. Papabravo

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    One register at a time.
     
  18. takao21203

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  19. spartai

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