memory cell simulation

Discussion in 'Homework Help' started by miklee, Mar 27, 2011.

  1. miklee

    Thread Starter New Member

    Mar 27, 2011
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    Good morning. I'm looking for a LTspice schematic of a cell memory to simulate. I was thinking in a cmos 6t sram. Memory simulation is a work for my thesis and I need a big help. Thank you so much
     
  2. Georacer

    Moderator

    Nov 25, 2009
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    This isn't a free homework service. You must post your attempt at your problem in order to receive help.

    Aside from that, a Google Images search of "6t sram cell" will produce many result. I think Wikipedia has an article about sram cells too.
     
  3. narasimhan

    Member

    Dec 3, 2009
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    There are separate ltspice websites having those simple simulations and tutorials
     
  4. miklee

    Thread Starter New Member

    Mar 27, 2011
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    My problem is how to set the simulation. On my book, on internet is easy to find a general schematic, but i don't know which kind how nmos/pmos use, which kind of source. My teacher said: "just find a schematic on internet and only made a parametric simulation"
     
  5. Georacer

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    Nov 25, 2009
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    I don't really think you care what NMOS/PMOS you will use. You might as well use an ideal device, or any foundry you like, just to prove the theory of operation.
     
  6. miklee

    Thread Starter New Member

    Mar 27, 2011
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    Ok I tryed to make the circuit: what do you think about? Vdd should be equal to V2? Vdd=V2= Pulse(...)?
     
  7. Georacer

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    Nov 25, 2009
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    Vdd is a constant power supply in all the digital circuits you will encounter.

    V2 is the controlling voltage "Word Line" that says whether this memory cell will be used or not. If it is HIGH (Vdd) you can read from or write to this cell.
     
  8. miklee

    Thread Starter New Member

    Mar 27, 2011
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    I setted values and started simulation, but don't work.
    Between the first and the second cycle of V(wl), V(q) should keep the high value, shouldn't it?
    V(q) sounds cut...

    settings:
    V1: PULSE(0 1.8 6ns 0 0 2ns 5ns)
    V2: PULSE(0 1.8 30ns 0 0 30ns 50ns 2)
    Vdd: 1.8V
     
  9. Georacer

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    Nov 25, 2009
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    Do the following corrections and re-post the graph, so we can analyse it better:


    • Reduce the input (bit) frequency. It is too fast for effective measurements. Half or 1/3rd frequency would be nice.
    • Make the wl signal steeper. A rise and fall time of practically zero would be good.
    • Finally tell us in which node you measure the internal states q and q'.
     
  10. miklee

    Thread Starter New Member

    Mar 27, 2011
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    I send a more detalied schematic that I done. I corrected the M5 pass-transistor and M2, M3 mos (source-drain inverted).
    Now the simulation works but I don't now how connect the M5 and M6 substrate. In this way works but without substrate connection...
     
  11. miklee

    Thread Starter New Member

    Mar 27, 2011
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    I solved the question, I connected correctly the substrate and now works.
    I have a question: which parameters I can change for a parametric simulation? The W and L of the inverters' MOS?
     
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  12. Georacer

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    Nov 25, 2009
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    I think it's universal that all PMOS substrates are connected to Vcc and all NMOS substrates on Ground. Try it out and see if the problem with the voltage reference persists.

    edit: I missed the thread's second page so this post is out of date.
     
    Last edited: Apr 1, 2011
  13. Georacer

    Moderator

    Nov 25, 2009
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    It depends on what you want to study. If you want to find the maximum feasible frequency you should play with it.
    If you want to study the response foundry-based, you could reduce L and W.
    If you want to study the response based on W, you could do it, to show how W affect rise and fall times.

    Keep in mind that as a general rule the two Word Line transistors should be twice as wide as the rest of them, in order to be able to write the bit state fast enough.
     
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