Meaning of Rds(on)

Discussion in 'General Electronics Chat' started by jaydnul, Oct 20, 2015.

  1. jaydnul

    Thread Starter Member

    Apr 2, 2015
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    This is where I'm confused. When a MOSFET is fully on it is in saturation Vds>Vgs-Vth AND Rds(on) is usually fractions of an ohm.

    Let's say:
    Vgs-Vth=5V
    Rds(on)=.01ohms

    That means Vds(minimum)=~5V, so Id=500A? Could someone tell me what I'm not understanding?
     
  2. mcgyvr

    AAC Fanatic!

    Oct 15, 2009
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    Rds(on) is simply the resistance from drain to source when the mosfet is fully on.
    Its used for calculating dissipation in the mosfet using I^2 R
     
  3. MikeML

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    The load that the FET is switching determines the drain current. Suppose that the resistance of the load is 1Ω. The drain current would be ~ (supplyvoltage-Vds)/1, where Vds is the voltage drop due to Ron.
     
  4. marcf

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    Dec 29, 2014
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    Pretty impressive part! Ids = 500 Amps with a Vgs of 5v. What's the part number?
     
  5. Papabravo

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    Feb 24, 2006
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    Vds cannot be very large if Rds(on) is in the fractions of an ohm range. The whole notion of being ON means there is very little voltage drop between the drain and the source. As Vgs approaches Vth from below the reseistance of the channel decreases and Id increases. At voltages substantially above Vth, the MOSFET is fully on, Vds is small and Id approaches its maximum practical value.
     
  6. ian field

    Distinguished Member

    Oct 27, 2012
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    Looks to me like you're getting your parameters confused.

    5V on the gate of a logic level MOSFET sounds plausible enough.

    I think if you developed 5V across the stated RDSon - it would most likely let the magic smoke out.
     
  7. jaydnul

    Thread Starter Member

    Apr 2, 2015
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    This is what's confusing. If Vgs is large and Vds is small, the FET is in triode mode not saturation. Is that not right?
     
  8. dl324

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    Mar 30, 2015
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    When Vgs is sufficiently above Vth, the MOSFET will be fully on and Rds(on) will be at it's minimum. Vds is determined by the supply voltage, load, and Rds(on).
     
  9. marcf

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    If P=IE, 500amps * 5Volts = 2.5KW. Like I said that is some impressive JFET.
     
  10. bertus

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    Apr 5, 2008
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    Hello,

    Have a look at page 2 of the attached application note.

    Bertus
     
  11. dl324

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    This thread is about an N channel enhancement mode MOSFET.
     
  12. MikeML

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    Oct 2, 2009
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    Perhaps this will help:

    Note that Vds is plotted on a log scale vs Vgs. Note that after the FET turns on, Id is mostly determined by R1. This FET has a Vth of 2V, and Rds of a few mΩ. Note that to get the advertised Rds, the Vgs has to approach Vth + several volts.

    132.gif
     
  13. Papabravo

    Expert

    Feb 24, 2006
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    That is wrong.
    By analogy to the Bipolar Junction Transistor.
    CUTOFF - No Collecter/Emitter Current flows, and Vce is a maximum and equal to the supply voltage in the Common Emitter Configuration. For a FET it means, no Drain/source Current flows, Vds is a maximum and equal to the supply voltage in the Common Source Configuration.
    SATURATION - Collector/Emitter current flows depending on the external load and power supply, Vce is a function of Collector Current and is usually a few tenths of a volt. For a FET it means what I said in the previous mode.
    In between those extremes on the DC and/or AC load lines at an operating Q-point established by biasing circuitry the BJT acts as an amplifier in a linear fashion. This amplifier amplifies current, that is small input currents produce large output currents. In between the extremes on the DC and/or AC load lines at an operating Q-point established by biasing circuitry, a FET also acts as an amplifier in a linear fashion. This amplifier works on small input voltages and produces output current like a triode vacuum tube did in an earlier era.

    What you call triode (pentode) mode is actually the area of operation between CUTOFF and SATURATION, even though channels in FETs don't actually saturate in the way that a bipolar junction does.
     
  14. jaydnul

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    Apr 2, 2015
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    The inequalities for the modes of operation of a FET are:

    Triode: Vgs-Vth>Vds
    Saturation: Vgs-Vth<Vds

    So what you're saying is that for really big values of Vgs, these equations don't mean anything? Where is that point defined?
     
  15. AnalogKid

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    You are assuming that all of the device can operate at all of its maximum parametric values at the same time. It cannot. The part has a max voltage, a max current, and a min resistance, but not all at the same time. So if it is rated for 100 V and 10 A, that does not mean that it can operate with 100 V Vds and 10 A Id at the same time. That would be 1000 W power dissipation in the device, and it would fail almost instantly. If the part is rated for 100 W, then when it has 100 V across it it can sink only 1 A before exceeding its thermal rating. Or it can sink 10 A, but only if Vds is less than 10 V. Voltage, current, and power are the three limits that must not be exceeded.

    ak
     
    Last edited: Oct 20, 2015
  16. Papabravo

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    Feb 24, 2006
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    I think it would help you greatly to draw a load line for a given circuit. We can assume we are talking about a common source circuit, but you have not explicitly stated that this is the case. I guess you don't agree that CUTOFF is a mode of operation.

    I would define that as Vgs << Vth, do you agree?
     
  17. jaydnul

    Thread Starter Member

    Apr 2, 2015
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    I understand there is maximum ratings and I understand that 500A is not going to happen. My question is about the equations that are supposed to (roughly) describe the behavior of the these devices. If the math is correct, then:

    Triode: Vgs-Vth>Vds
    Saturation: Vgs-Vth<Vds

    And when Id starts flowing and Vds starts decreasing, by the math, the device should go into triode mode (the voltage drop across the D-S is much lower, and remember from above: Triode: Vgs-Vth>Vds).

    I'm asking why these equations are not properly describing the behavior of a FET.
     
  18. jaydnul

    Thread Starter Member

    Apr 2, 2015
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    [​IMG]

    MikeML's plot illustrates my question just fine. When the gate voltage is 5V, Vd is fractions of a volt. The math says this should be a FET in triode mode, Vgs-Vth>Vds.
     
  19. Papabravo

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    Feb 24, 2006
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    I can't answer your question because I have never seen them before with respect to the operation of a FET, and I'm not sure they are universally true without qualification. I think I learned a different way of looking at things that has served me well in designing FET based circuits. Vth is definitely the key concept. That and the equivalent circuit of a FET that shows that is an input voltage controlling an output current. Other considerations are obvious from the AC and DC load lines. If you can match those inequalities to the graphical picture then you've got something useful. Otherwise not so much. I know I'd rather look at a load line on a set of characteristic curves than try to remember a set of inequalities.
     
  20. jaydnul

    Thread Starter Member

    Apr 2, 2015
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    Can anybody address post #18?
     
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