maximum delay path in 4*4 multipler circuit

Discussion in 'Homework Help' started by athulascc, Mar 13, 2015.

  1. athulascc

    Thread Starter Member

    Aug 15, 2014
    I have marked path
    is that one of maximum delay path? Capture2.JPG
  2. WBahn


    Mar 31, 2012
    Looks pretty reasonable.

    How might you confirm that your answer is correct?

    What is your reason for concluding that it is the path ending with P7 and not the one ending with P6 that is the max delay?

    What are the various delay times that come into play? What would be required in order for a different path to be the max delay? How reasonable would it be for those conditions to apply?