Max Propagation Delay temp or path?

Discussion in 'Homework Help' started by Tera-Scale, Jan 22, 2011.

  1. Tera-Scale

    Thread Starter Active Member

    Jan 1, 2011
    164
    5
    I am asked to find the maximum propagation delay of a subtractor i designed by referring to the data sheet of each ttl IC. Do I have to take it in terms of temperature effecting the the operation (from datasheet) or is it a matter of the longest path (number of gates to encounter) for a logic state to be established at the output?

    Brandon
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    You get the best answer by checking with the instructor. Longest path and worst case delay is probably good enough.
     
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  3. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    When I am asked to do such calculations, they want me to use the longest logical path and the typical IC delay, the temperature effect not being taken into account.
     
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  4. Tera-Scale

    Thread Starter Active Member

    Jan 1, 2011
    164
    5
    I checked with my lecturer and it was exactly as you said - the temperature shouldn't come in here and it is important that if I used the typical or the worst case scenario .. it should be noted down.
     
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