# Master Slave D Flip Flops and Mas. Sl. SR Flip Flo

Discussion in 'Homework Help' started by aliscafo, Apr 17, 2004.

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1. ### aliscafo Thread Starter New Member

Apr 17, 2004
2
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Hi,

I am reading my textbook about Flip Flops and I dont understand why a Master Slave Flip Flop
made of D latches is edged triggered and why when it is made of SR latches, it is pulse triggered

2. ### mozikluv AAC Fanatic!

Jan 22, 2004
1,437
1
hi,

check my post reply to "drnath" re logic devices

3. ### mozikluv AAC Fanatic!

Jan 22, 2004
1,437
1
hi aliscafo,

hope you have already read the reference material i have posted. besides i can't seem to believe that your book does not fully explain the function of a JK Master -Slave Flip-flop or maybe you just find it hard to understand.

i hope you don't mind the little lecture since this is the "homework section". as i have always said, "learn the basics by heart" lets take the case of flip-flops, if you don't know how it did come about and the heart of that chip are all transistors and diodes, it will come to your mind so many hows and whys and never be able to explain it. knowing a bit of history of those kind of chips will help you a long way. lucky for you guys you still have teachers to explain for you.

now back to the flip flop - basically there are 2 circuit blocks composing of SR flip flop that reacts to the SET & RESET inputs when the ENABLE pin is in low state. When E is in a high state they can't change state. Say a logic high onSET makes Q to go high, while a high at RESET makes Q to go low, provided that ENABLE pin is low. It must be remembered that you cannot make SET & RESET go high at the same time or the output will be in an unpredictable state. the 2 SR flip flops are enabled so that the MASTER responds when E is in low state and the SLAVE responds when E is in high state. the output of the SLAVE is fed back to the MASTER. Again it must be remembered that the MASTER & the SLAVE will not race with each other because the 2 are never simultaneously enabled and this made sure by an inverter in the chip.

it must also be noted that the S of the MASTER will not go hig when J is low or R will not go high if K is low. Now when J & K are in high state the complement of the present state is fed back thus the flip flop will toggle when E is driven high.

most JK flip flops are edge sensitive like D flip flop and reacts to the state of the input at the time of the clock edge

we will deal with you other question the next time, am already tired of pounding the key boards, man am i that old already?

Nov 17, 2003
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5. ### shash New Member

Apr 16, 2004
3
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The way I understand it, it's to prevent a change without reason.

Let's take an SR flip flop with S=1 and R=0. The output of this thing has to be 1, right? And if it's pulse triggered, for the entire duration of the pulse, the inputs are the same and thus the output does not change automatically.

Now, let's try a T flip flop with T=1. Remember, T is just a JK with J=K. So, this acts as a toggle. If it's pulse triggered, for the entire duration of the pulse, it just keeps toggling. Imagine reading it, and finding that your output keeps changing, even though your input is constant. This can be a major problem with many devices that need this constant output.

And that's why an SR latch based flip flop is pulse triggered (because it doesn't have this condition) and a JK latch based flip flop is edge triggered (to avoid this condition).

Hope that helps!

6. ### Dave Retired Moderator

Nov 17, 2003
6,960
143
Not to challenge your whole reply as its seems on the face of it correct. But if I remember correctly for a basic S-R bistable with S=1 and R=0, the output Q+ =0, not 1.

For an output of Q+ =1, S=0 and R=1 or S=1 and R=1 where Q was already equal to 1 prior to the transition.

In other words the output of the S-R bistable can only go to 1 when R goes high this is know as an active low version, i.e. the device is activated by taking the appropriate input low (S changes 1→0 to SET and R changes 1→0 to RESET).

We can create an active high version which would give S=1, R=0, Q+ =1, however we will need to invert the inputs from S and R. This obviously works in the opposite way to the above version.

7. ### shash New Member

Apr 16, 2004
3
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I was talking of the active high implementation (using NOR gates, IIRC). Then you don't invert it.

If you design it as a bistable multivibrator, you have to invert it, of course...

8. ### aliscafo Thread Starter New Member

Apr 17, 2004
2
0
I would llike to thank you all for your help.
I had my exam on Thursday and it went pretty well.
Thanks a lot. If you have more info. since I really like
this class feel free to post some more. I will take a look
regularly.