Good day!
Currently, I'm analyzing Mandal-Sarpeshkar rectifier (found in an IEEE paper) to be used in our project about Radio Frequency energy harvesting. The configuration of a one-stage and N-stages are shown in the attachment.
The input is differential, and the output is across the nodes VH and VL. The MOS transistors operate in linear region.
The operation of a one-stage is as follows. When Vin+ is high and Vin- is low, M2 and M3 turns on and I've calculated that
The same output voltage is obtained when Vin+ is low and Vin- is high and M1 and M4 are on.
My questions/clarifications are:
1. Is the output equal to the amplitude of Vin+ or Vin- minus the voltage drops across the two active transistors? or is it twice the amplitude minus the voltage drops?
2. In order to function as a multiplier, cascading N-stages is done and the output is
3. Why does VL of first stage is grounded?
4. Why are there capacitors at the input of the other stages and the first stage doesn't have?
5. Am I correct in thinking that Vout is now across VH of the last stage minus VL of the previous stage?
Thank you in advance!
Currently, I'm analyzing Mandal-Sarpeshkar rectifier (found in an IEEE paper) to be used in our project about Radio Frequency energy harvesting. The configuration of a one-stage and N-stages are shown in the attachment.
The input is differential, and the output is across the nodes VH and VL. The MOS transistors operate in linear region.
The operation of a one-stage is as follows. When Vin+ is high and Vin- is low, M2 and M3 turns on and I've calculated that
Vout=VH-VL=2|Vin|-(Vds,n + Vsd,p)
The same output voltage is obtained when Vin+ is low and Vin- is high and M1 and M4 are on.
My questions/clarifications are:
1. Is the output equal to the amplitude of Vin+ or Vin- minus the voltage drops across the two active transistors? or is it twice the amplitude minus the voltage drops?
2. In order to function as a multiplier, cascading N-stages is done and the output is
Vout=N[2|Vin|-(Vds,n + Vsd,p)]
I cannot find a way to prove the above equation.3. Why does VL of first stage is grounded?
4. Why are there capacitors at the input of the other stages and the first stage doesn't have?
5. Am I correct in thinking that Vout is now across VH of the last stage minus VL of the previous stage?
Thank you in advance!
