Managing Asynchronous Memory Access

Discussion in 'The Projects Forum' started by shaqywacky, Aug 5, 2012.

  1. shaqywacky

    Thread Starter Active Member

    Apr 1, 2009
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    Hi everyone!

    I've been working a homebrew computer project for a while and I've run into a problem when I try to write to memory.

    The problem is just how to manage setting the write and chip select pins at the approiate time. What I need is for the chip select pin to be low(IE do not allow any reads or writes) until the write pin goes high(initiating a write) then I need the chip select pin to wait a little amount of time to allow the address pins to settle then, have the chip select pin go high. I also need the chip select pin to go low before the write pin goes low.

    I attempted to do this with a 555 timer in monostable mode. I connected the trigger pin of the 555 timer to the write pin so that when the write pin was put high, the 555 timer would delay the chip select pin for a little while and also turn it low after a determined amount of time. There are a few problems with this method. First I need an edge detector which I have had trouble implementing. Second, there still exists a point where two signals must arrive is a certain order.

    So I wondering if anyone has a better way to do this. To be perfectly clear what it is I'm trying to do, here a little diagram:
    access.png

    I would like to keep this as simple as possible because of limited breadboard space. Also, I don't want to use anything like microcontrolers and such. I'd like to just use simple logic.

    Any input appreciated. :)
     
  2. Papabravo

    Expert

    Feb 24, 2006
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    What you want is a gray code counter and a decoder or a shift register and a decoder. You start by loading the counter or shift register with an initial value. At each successive clock pulse you "count" or "shift". On the outputs of the counter or decoder you decode the various states and you can guarantee one whole clock pulse between edges. After the final state you hold the counter or shift register in an "idle" state until the next trigger event.

    http://en.wikipedia.org/wiki/Gray_code#Gray_code_counters_and_arithmetic

    PS You use a gray code counter because only 1-bit chages at each clock pulse.

    PPS I'm flabbergasted that you even considered using a one-shot (monostable) for this purpose. The drawback as you have discovered is that you cannot reliably control the location of the trailing edge. Synchronous design is the only way to go for this application.
     
  3. shaqywacky

    Thread Starter Active Member

    Apr 1, 2009
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    Ok, thanks. I'm going to have to do a little reading on gray code. And from the looks of it I'll probably have more questions. Thanks again.

    Hahaha, yes, I have very little formal education in these things. I usually try to solve it my way and when that doesn't work, I find out the right(better) way.
     
  4. MrChips

    Moderator

    Oct 2, 2009
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    A 555 timer circuit is not appropriate for this application and is way too slow.

    It would help if you gave us some part numbers.

    What is the part number of your memory chip?
    What chip are you using to access the memory chip?

    For a homebrew system, typically one would simply use a time-state generator consisting of a binary counter (2 to 4 bits) and a decoder such as a 74138.
     
  5. #12

    Expert

    Nov 30, 2010
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    You'd probably feel the same about the difference between your education and mine :)

    and that is one of the reasons I contribute. I get to learn about people that are very different from me, and yet very smart. Keep up the good work with the ones and zeroes. I'll take care of the analog stuff. :D
     
  6. Papabravo

    Expert

    Feb 24, 2006
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    Funny you should mention that because analog computers came before the digital variety and feedback control systems, like the fly ball governor, came before either one. So I'll agree that we can both take care of anything we feel comfortable with:). There is a place for one-shots(monostables), but memory is not one of those places.
     
  7. #12

    Expert

    Nov 30, 2010
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    Eep! Maybe I should have said I'll take care of the chicken coop doors. Didn't mean to step on your toes but, I was chasing down a nanoamp level error in an analog circuit yesterday, and it was fun.
     
  8. Papabravo

    Expert

    Feb 24, 2006
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    No toes have been stepped on that I'm aware of. Very few of us are 1-dimensional. Come to think of it, I haven't visited Flatland recently either.

    http://en.wikipedia.org/wiki/Flatland
     
  9. shaqywacky

    Thread Starter Active Member

    Apr 1, 2009
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    @papabravo
    Ok, I see how gray code solves the memory access for sequential reads and writes. But I don't see how to use it for random memory access. I think you were describing it in your post but I don't quite understand. I don't want to ask you to explain it again, so is there a name for this set up that I could read about.

    @MrChips
    Oh, I don't plan for this to be particularly useful. More like a proof of concept. My set up right now only has a 4-bit data bus and 16-bit instruction bus. So the max amount of instructions right now is 16. So I plan for it to run pretty slow(like really slow, 1Hz at the lowest and probably 1kHz at the highest) so that I can see it run in real time.

    The memory chip is HM6116ZP-4. I'm using a bus driver to access the chip. I'm at work right now, so I get the part number in a little while.

    Also, what is a time-state generator? I tried goggling but I can't find anything about it.
     
  10. Papabravo

    Expert

    Feb 24, 2006
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    You missed the point. The Gray code counter is not for the address portion of the inputs to the memory it is used to generate the control signals, Chip Select(CS-bar), Read (RD-bar), and Write (WR-bar). Read (RD-bar) can also be labeled Output Enable (OE-bar).

    Those outputs are decoded (ie derived from a combinatorial circuit) from the states of the gray code counter OR shift register.

    For example say we have a counter/shift register with 8 states. Then we say Chip Select is low for states {1,2,3,4,5,6} and high for states {0,7}. then we say Write is low for states {3,4,5} and high for states {0,1,2,6,7}. Those signals overlap in the way required by the static RAM chip you are using and that is what a microprocessor would do.

    The reading you should do is on the Finite State Machine (FSM). There are two subspecies called the Moore Machine and the Mealy Machine.

    http://en.wikipedia.org/wiki/Finite-state_machine

    Good Luck
     
  11. shaqywacky

    Thread Starter Active Member

    Apr 1, 2009
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    Ah, ok. I think I understand. That is much better than the solutions I had.

    Thanks.
     
  12. MrChips

    Moderator

    Oct 2, 2009
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    Take a 3-bit binary counter, such as a 74LS161. Connect QA, QB, QC outputs to the A, B, C inputs of a 3-to-8 decoder such as a 74LS138.

    You now have a time-state generator that has 8 states defined.

    We can number the states T0, T1, T2, T3, T4, T5, T6 and T7.

    As Papabravo suggests, you can select during which time-states you wish each of the control signals CE, WE, OE to be active.
     
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