# Make circuit from a table truth!

Discussion in 'Homework Help' started by jonhh, May 30, 2011.

1. ### jonhh Thread Starter New Member

May 30, 2011
4
0
Hello,

I have stuck on this!

i have this table truth:

S CLK
0 0 -> 1
0 1 -> 1
1 0 -> 0
1 1 -> 0

i want to design a circuit, which implements the above table. Can you help me? i can use whatever gate i want!

thank you!

2. ### debjit625 Well-Known Member

Apr 17, 2010
790
186
From your truth table you can get the Sum OF Product (SOP)

OUT = (S' CLK') + (S' CLK)

from this we can get into this circuit (I have not checked for any further
simplification)

If you didnt understood then you can read this section

Above section is from the free ebook at AAC,at the top of this webpage you will get all the link (Tabs) for the ebook.

Good Luck​

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3. ### Georacer Moderator

Nov 25, 2009
5,142
1,266
Debjit, you need sometimes to look at the big picture, outside of formalitites. The boolean function at question is F=S' (F=NOT(S)).

I 'd like to ask the OP though whether he wanted to build a circuit that would be clock triggered. This insn't the case in this function.

Last edited: May 30, 2011
4. ### debjit625 Well-Known Member

Apr 17, 2010
790
186
You are very much correct, and I also know that. Its the reason I wrote.
I think he should do this by himself, but anyway here is how

Out = (S' CLK') + (S' CLK)
Out = S' (CLK' + CLK)
Using the property (A + A' = 1)
Out = S'

Even some of us dont have to do this simplification, just by looking we could come up by the result. But the OP asked...
So I thought it will be right to show him the SOP or POS methods. And also by this way I could refer him to AACs e-book.

5. ### jonhh Thread Starter New Member

May 30, 2011
4
0
Yes, i want to clear a (positive triggered) FF when the S is 0 and this action must be done with the clock and not when i "push the button s"...

6. ### jonhh Thread Starter New Member

May 30, 2011
4
0
i just thought something...
if iwant to clear my ff, when S=0 and in the possitive rise of the clk then the table truth is this ????

S CLK
0 0 -> 0
0 1 -> 1
1 0 -> 0
1 1 -> 0

I say that because the CLK before it takes the value 0, it was 1. So this change(1->) did happend in the negative edge of the clock and because the ff is positive triggered nothing will happend...

am i right?

Last edited: May 30, 2011
7. ### Georacer Moderator

Nov 25, 2009
5,142
1,266
Unfortunately no. All the Flip Flop packages that I know of, have Set and Reset pins that work asynchronously. That means that the moment you apply a '0' (in most cases) in the Reset pin, the FF will instantly go to '0'.

If you want to Reset your FF in synch, you may be better off intervening another D-FF between your Reset button and the Reset pin. The signal will reach the FF that has to be reset in the next clock cycle.

@Debjit
You put it in a way that I thought that you actually didn't simplify it anymore in your head. I didn't get that you were testing the OP.

8. ### jonhh Thread Starter New Member

May 30, 2011
4
0
thank you all!!!!!!!

9. ### vinay arora New Member

Jun 3, 2011
15
0
but can we apply simply k -map to make the circuits from above truth table.

10. ### Georacer Moderator

Nov 25, 2009
5,142
1,266
We did. But it was a simple one and we did it in our heads.

11. ### pistnbroke Member

May 9, 2011
32
1
so you have done this guys homework and propelled him toward what will be a worthless Phd .....

will you people never learn ...help those who help themselves ...

12. ### Georacer Moderator

Nov 25, 2009
5,142
1,266
If that was his Phd, then it will take much more to finish it. We generally hold very high the principle of "help yourself first" in AAC.

13. ### debjit625 Well-Known Member

Apr 17, 2010
790
186
Ok now people are getting their PhD over NOT gate????

By the way whats the name of the University,may be I could get one..... PhD.

Georacer likes this.