# LVDS in FPGA

Discussion in 'General Electronics Chat' started by Rahul Soni FPGA, Feb 28, 2014.

1. ### Rahul Soni FPGA Thread Starter New Member

Feb 28, 2014
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0
HI,

I am Rahul

How LVDS works that I know , but only theory.

My Quest: if I apply +2 to +input(i1) and -2 to -input (i2) at sender side then what is output at receiver side.

is it like : vout = i1 - i2

if yes then vout = 2 - 2 = o... how its possible

Last edited by a moderator: Feb 28, 2014
2. ### kubeek AAC Fanatic!

Sep 20, 2005
4,689
806
That would be 2 - (-2) = 4, just like any other differential signalling. Seems your theory is lacking a bit as well.
Anyway, what does this have to do with the e-book? I doubt that it covers LVDS or FPGA.

3. ### Rahul Soni FPGA Thread Starter New Member

Feb 28, 2014
4
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if I send 2v & -2v volt through LVDS I/o of FPGA then receiver LVDS FPGA got 4v ?

what happen in receiver side ?

4. ### MrChips Moderator

Oct 2, 2009
12,635
3,453
As kubeek indicated, you need to understand differential signaling a bit more.

RS-422, RS-485, USB are all examples of differential signaling.

What is important is not that 2 - (-2) = 4, but the fact that the signal to noise ratio (SNR) and common mode rejection ratio (CMRR) are improved significantly.

Any noise that is common to both signal lines is eliminated by subtraction. The receiver can better separate the signal from noise.

5. ### Rahul Soni FPGA Thread Starter New Member

Feb 28, 2014
4
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ya I know that SNR and CMRR that all stuff, but I feel to much confusion about vout =4 at rcver side.

how Receiver react with 4 volt ? recevicer consider 4 volt or 2 volt .

I know noise will subtract but wat about voltage ?

receiver accept (4 volt) more voltage than sender in LVDS

6. ### atferrari AAC Fanatic!

Jan 6, 2004
2,666
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Noise is also a voltage, let's say...

7. ### MrChips Moderator

Oct 2, 2009
12,635
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I already told you to forget the 4V.
LVDS chips for computer systems do not use -2V.
The purpose of LVDS is to transmit and receive data at very high data rates and thus LVDS buses and data paths must be treated as transmission lines.

8. ### Rahul Soni FPGA Thread Starter New Member

Feb 28, 2014
4
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Thank you very much

Now I understood wat you are trying to explain.

can you forward me LVDS internet link to understand deeply with example?