LTSpice "R" Simulation

Discussion in 'General Electronics Chat' started by Prabu1004, Apr 22, 2013.

  1. Prabu1004

    Thread Starter New Member

    Apr 17, 2013
    2
    0
    Hi,

    Simulated transient analysis of a simple Resistor divider network with the below settings using LTSpice. From simulation, observe that Voltage & Current are 180 deg out of phase. Actual relationship is in-phase for R network between Voltage & current.

    R1=1K, R2=1K
    Vin = 1V peak to peak, 60Hz & 10V offset

    Attached herewith the Simulation result & R network.
    Green --> Input Voltage
    Red --> Current drawn from Source Vin
    Blue --> Output Voltage.

    Regards,
    Prabu.
     
  2. crutschow

    Expert

    Mar 14, 2008
    13,001
    3,229
    The reason is the direction that LTspice assumes for positive current. If you hold the cursor over the resistor you will observe that the current arrow is pointing to the left. This means that current through R_1 will plot as negative for current going from left to right, as is the case for your circuit. If you draw the circuit as a mirror image, you will get a positive current for positive voltage.
     
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