LTspice model for CD4060B 14-stage binary clock/counter

Discussion in 'Digital Circuit Design' started by Alec_t, Aug 15, 2016.

  1. Alec_t

    Thread Starter AAC Fanatic!

    Sep 17, 2013
    5,773
    1,103
    Attached are LTspice simulation model files I made for this popular IC. The model is not a stand-alone one; it requires use of input filter and output driver models found in the CD4000.lib and CD4000_v.lib libraries freely downloadable from the Yahoo LTspice User Group. The model is a development of the CD4020B model found in those libraries, with functional additions and modifications.
    To use this new model you will need one or both of those libraries installed in the sub folder where LTspice can find them. Copy and paste the contents of the .txt file into the library/ies. Put the .asy file in LTspice's /lib/sym/CD4000 folder. I've included a .asc Test file. Have fun :).
     
    Sinus23 and wayneh like this.
  2. wayneh

    Expert

    Sep 9, 2010
    12,090
    3,027
    Are you cross-posting this at Yahoo as well?
     
  3. ci139

    Member

    Jul 11, 2016
    341
    38
    my oversimplified I/O goes for now as that
    i must check yours ... in operation ...

    BTW it's good someone has nerve to test-compile the more complex chip models - though i probably 'd do it myself anyway to be sure it does what it should ...

    if there 'd B a verification history available for Alec_t.CD4000.lib
    with basic function demos - i'd consider using it , Hi o_O
     
  4. Alec_t

    Thread Starter AAC Fanatic!

    Sep 17, 2013
    5,773
    1,103
    Haven't done as yet. The last time I posted models there (for LM3914 and LM3915) they got removed by the mods. Don't know why.
    Well no-one's verified me as far as I know! :). As for the CD4000.lib library, that's well established and nothing to do with me.
     
  5. ci139

    Member

    Jul 11, 2016
    341
    38
    about the problem - as the copy-paste is very trendy in computer age the documents may morph or mutate in a long way from designer board to datasheet print-form graphic designer - the least does not usually grasp the materials function he/she is editing - so a primary soure of error - the next ones are the enthusiast wackos who may in a rush and due technical peculiarities and unpredictable behaviour of simulation software pass the 2-nd generation errors or peculiar functioning in some specific situation - so what is needed to be verified is not that we exist o_O - but rather that the chip model works as close to real thing as possible or as it does :confused: !!!
    for that usually you dumbly test all chip model functions and transitions - and convince that they are those the real chip have (or fall close enough)
    then you add a notice to your model (perhaps as About-MyModelName.txt) that verified to function in :: votage range , frequency range, output loading (capacitive resistive inductive) not deviating more than ±err % of nominal average of the real chip at the same range , blah , blah , blaah . . . the user of this model must realize the limitations of simulation software, and the intended use of the model is for illustrative / educational purposes . . . the user of this model needs to make sure by itself wheather useing this model for some other aplication is consistent enough
     
  6. Alec_t

    Thread Starter AAC Fanatic!

    Sep 17, 2013
    5,773
    1,103
    If I understand you correctly then no, I haven't verified the model against the real-world IC as I don't have the facilities to do so. But I'm not aware that any other models in the CD4000 series (including the CD4020B which I relied on) have been verified according to your criteria either. Do you have evidence that they have?
     
  7. eetech00

    Active Member

    Jun 8, 2013
    648
    110
    Hi

    I don't know about anyone else, but I test the model before I use it, no matter what the disclaimer says. ;)
     
Loading...