Hi!
What are the things I should concentrate when I designing the low pass filter of the feedback loop in a PLL?
Any help would be appreciated.

 

It depends upon the type of phase detector, the capture range of the loop, and the desired response time of the loop to acquire a signal.

 

Hi
What do you mean by "type of the phase detector" and "capture range" ?

Actually I am going to construct a low pass filter for fractional-N PLL.http://en.wikipedia.org/wiki/Wikipedia:Disputed_statement

 

There are different types of phase detectors, some analog, some digital, some in between.

A XOR gate is a phase detector, for example. So is a hetrodyne mixer.

 

Here's a short primer on phase-locked-loops. That should answer some of your questions.

 

I am using 74F85 magnitude compactor as the phase detector.
Reference freq is 50 kHz.
Then what is the capture range?
(Lock range of the PLL is 70MHz to 150MHz)
What would be the cut off frequency of the low pass filter?

 

We need to see your circuit diagram and your requirements for the loop performance to give intelligent answers to your questions.

 

Its a fractional-N PLL for a FM tranmitter which has a transmission range of 88MHz to 108 MHz with a channel spacing of 100 kHz. MAX2606 is using as the VCO. Center frequency is set as 100 MHz. Divided by N counter is a programmable one to achieve the desired frequency at the VCO output. Vtune of the VCO ranging from 0.4 V to 2.4 V. I already mentioned about the phase comparator and the reference freq. in the previous post.
Anything else to know?
If you need a circuit diaram of the PLL, I can attach here. Let me know.
I need both accuracy and the stability of the system.

 

A circuit diagram would be good so the filter location and type can be seen.

 

Output of the T flip flop ;74LS109 which is coming from the JP2 and the reference frequency are the connected to JP1 and outputs of the JP4 is connected to the antenna and to the JP3. Four down counter ICs are 74F192 decade up/down counters. Hope this diagram helps you to give a more specific solution.

According to the calculations reference frequency is 50 kHz and count range is 880 to 1080. Each ABCD inputs of 74F192 are connected to 4 position DIP switches and hence I can change the count of this divided by N counter.

I added just an active low pass filter and struggling to choose suitable values for the resistors and capacitors of the low pass filter.

 

You apparently posted this as a JPEG image, which makes it very fuzzy. Better to use a GIF bitmap image.

You use a 7485 magnitude comparator but only use two of the inputs. Why not use a XOR gate as a phase detector as is typically done?

You also include a integrator in the loop (the 741) which can make it more difficult for the loop to stabilize due to integrator wind-up. I believe an integrator is only needed if you require zero phase error at lock and I don't see that as a requirement for your system.

You also have C2 and C3 in parallel. You only need one cap there.

Here's a tutorial on PLL stability that should help you calculate the filter values you need.

 

If you are using this as a FM demodulator (which is a common application) you will need a higher fidelity Op Amp, since it will output a audio signal.

Only reason I think this is because of the frequency range, the FM band.

 

According to the Vtune vs Frequency graph of the datasheet of MAX2606, maximum Vtune input voltage is around 3V. The phase comparator's maximum output voltage is Vcc (5V). Then do I need a gain less than 1 in this loop filter?
Since I am constructing a frequency synthesizer, will this construction give the desired output frequency according to the relevant count of the divided by N counter (center frequency is set as 100MHz from the 390nH external inductor)?

 

No replies.
Do I really need to consider about the DC gain which outputs to the input of VCO when I constructing a PLL?

 

Remember that this is an international forum and you may have to wait 12 hours to catch others from the other side of the globe.
Secondly, PLL is not everyone's area of expertise.