Hello everyone,
Could some one please tell me what cutoff frequency values of a filter are generally used for filtering a DC input.If it terms of Hertz,how close would it have to be to zero,without loosing the signal?

Regards,
Arun

 

When talking about filtering a power supply, I don't think of it as a low-pass filter, rather I tend to think of it as how much charge do I have to store in the filter capacitor before the next full-wave rectified pulse comes along to replenish it...

 

Your question cannot be answered the way you have stated it.

What is your signal?

What is the criteria for losing the signal?

All of your responses must specify actual values.

 

Say what? A DC input has no information content so there is nothing to filter. In terms of realization, a low pass filter would have component values that would be difficult to realize.

 

A DC voltage is independent of frequency so it is not required to filter it
but if that was a rectified voltage(say from a full-wave or a half-wave rectifier), filtering would become necessary and the cut-off frequency depends on the input AC voltage used for rectification

 

Hello everyone, perhaps i should have been more clearer,my signal is a pure DC,generated from an LM323, which is powering a micro-controller.No Vreg DC value is perfect and it will carry some noise along with it.Now i could just use a decoupling capacitor near the LM323,but by my understanding the cap here is not used to protect the signal from noise ,but to prevent it from generating noise as rapid changes in the current consumption from the Vreg occurs.
Can't i use a low pass filter here to filter out any unwanted AC noise instead,for which i need a minimum cutoff value?

 

Hello everyone, perhaps i should have been more clearer,my signal is a pure DC,generated from an LM323, which is powering a micro-controller.No Vreg DC value is perfect and it will carry some noise along with it.Now i could just use a decoupling capacitor near the LM323,but by my understanding the cap here is not used to protect the signal from noise ,but to prevent it from generating noise as rapid changes in the current consumption from the Vreg occurs.
Can't i use a low pass filter here to filter out any unwanted AC noise instead,for which i need a minimum cutoff value?

No. This is not AC noise. This is signal generated by oscillation of the feedback control system attempting to regulate the output DC voltage. You do not filter out this oscillation. You need to stop the oscillation in the first place.

 

There is no, "standard" noise in a DC supply and the DC power pin of an IC is not its signal input pin.
Just place a 10 uf capacitor and a 0.1 uf ceramic capacitor across the power terminals of the microcontroller. That will fix the problem in both directions.

Peek at this: http://forum.allaboutcircuits.com/threads/decoupling-or-bypass-capacitors-why.45583/

 

Hello everyone, perhaps i should have been more clearer,my signal is a pure DC,generated from an LM323, which is powering a micro-controller.No Vreg DC value is perfect and it will carry some noise along with it.Now i could just use a decoupling capacitor near the LM323,but by my understanding the cap here is not used to protect the signal from noise ,but to prevent it from generating noise as rapid changes in the current consumption from the Vreg occurs.
Can't i use a low pass filter here to filter out any unwanted AC noise instead,for which i need a minimum cutoff value?

No, the source of the noise is the uController itself. It is a digital device, so the noise is generated by the transient current pulses that flow in/out of its Vdd and Vss pins as its internal nodes switch. You need to store energy right across the Vdd and Vss pins (in a Bypass capacitor), with the shortest (lowest inductance) possible leads.

 

Thanks guys,my initial thoughts were to put a tantalum and ceramic cap across the signal,i had this idea of a filter here and wanted to confirm it you you guys.
Is this same true for a varying DC,i mean for signals that would be given to an adc. I have a digital filter incorporated inside my controller, but to avoid any kind of aliasing effect ,should i have a filter before the adc samples the signal?

 

...
Is this same true for a varying DC,i mean for signals that would be given to an adc. I have a digital filter incorporated inside my controller, but to avoid any kind of aliasing effect ,should i have a filter before the adc samples the signal?

When sampling a time-varying signal with an ADC, you always need to have a low-pass filter ahead of the ADC which cuts off frequencies above half the sampling rate. See the Nyquist Theorem.

The amount of attenuation required at the sampling frequency is usually much more than a simple one RC filter can provide.

Please describe what you are measuring and how the actual ADC sampling rate.

 

An anti-aliasing filter does generally need to be in front of an ADC with a rolloff as low as possible (as determined by the highest signal frequency) but no higher than 1/2 the ADC sample frequency since anything above 1/2 Fs will be aliased and appear as a lower frequency at the ADC output.
The degree of rolloff (filter order) is determined by the amount of noise above the highest frequency of interest and how close that frequency is to 1/2 Fs.

 

Hello there,

Are you trying to reduce noise from the power supply voltage regulator or are you trying to reduce noise in the signal being measured by the ADC unit?

These two require two or three different approaches.

First, if it is the regulator, then a bypass cap is required, usually something like a 1uf to 100uf electrolytic in parallel with a 0.1uf ceramic.

If it is the signal to be measured, then an RC low pass filter could be used. The cutoff frequency must be high enough to allow the signal to get through but low enough to reduce the noise.

If it is the ADC reference voltage, then again an RC low pass filter could be used. In this case though you want the 'cutoff' frequency as low as possible, so maybe a 10uf in parallel with a 0.1uf, and a somewhat lower value series resistor (10 to 100 ohms but depends on the current draw of the reference input pin).

 

I am trying to do both.The decoupling capacitors did the trick in the first case.The noise level is slightly lower than before.
As for the dc signal which is to be measured ,the signal is a solar panel voltage which varies throughout the day.(0 to 5v)
I have configured my controller to sample at 94.33kHz(sampling period is about 10.6us),so that means i should have a filter with a cut off frequency of about 47KHz or less?

 

I am trying to do both.The decoupling capacitors did the trick in the first case.The noise level is slightly lower than before.
As for the dc signal which is to be measured ,the signal is a solar panel voltage which varies throughout the day.(0 to 5v)
I have configured my controller to sample at 94.33kHz(sampling period is about 10.6us),so that means i should have a filter with a cut off frequency of about 47KHz or less?

No, you should look at the real frequency components you are trying to measure. If there was an anti-aliasing low-pass filter with a 1Hz cutoff, would you be missing anything that is happening because the sun comes out from behind a cloud, or if you move the panel?

Here is how I would do it: Dirt simple single-pole RC filter with a 1Hz corner frequency. You would want the attenuation at the AD input to be about 1/2bit at the AD sampling rate. If you are using a 12bit AD with a full-scale of 5V, then you want the attenuation to be 5/(2*2^12) = 5/8192, which is -65db. I created the following little sim to illustrate this:



Reading off the plot, if the sampling rate is > 10k samples/s, then you are good to go... The noise being sampled is less than 1/2bit out of 12bits of resolution. If your AD has fewer bits, or a different Vref, you can do the math.

 

Thank you for such a detailed reply Mike,
I have finalized some values based on my circuit requirements,please verify if i am not missing anything
I have set my adc to sample at about 95KHz.Configured to work in 10 bit mode.

So my signal to noise ratio that satisfies Nyquist theorem is 20log(3.3/2*1024) = -55dB
The cut off frequency for my filter that i have selected is 1.575Hz.
I did a simulation of my own in LTspice.

So if my sampling rate is more than 4KHz(which it is) ,then there is no chance of any aliasing.
I would have to still test it with an oscilloscope, but correct me if i am wrong anywhere.
Arun

 

That will work.

I am curious, though. Your plot doesn't match the simple RC you show in the schematic?

 

That will work.

I am curious, though. Your plot doesn't match the simple RC you show in the schematic?

How so,i plotted it again and i g0t the same bode plot.

 

What are you using for C2? If you click on it, is it a pure capacitance, or does it have some parasitic series resistance or inductance?

 

Ah yes ,now i see it ,the cap which i had selected had some internal resistance.

Changed it to 0 and got this:


Thanks Mike for all your help
Arun