# Logical function of "active high" switch circuit

Discussion in 'Homework Help' started by J_Rod, Sep 8, 2015.

1. ### J_Rod Thread Starter Member

Nov 4, 2014
109
6

Good evening,

The circuit implements only "active high" switches, and I am asked to find the (positive) logic function for the OUT node. The paths to ground I found were when each of these terms is HI voltage (transistor is "on" and switch is a connected circuit): EFG, BCD, ABC, ACE, CDE, BFG. In the truth table, any minterms with these combinations of HI voltage, logical 1, will have a LO voltage for OUT, or logical 0 in the truth table. And that is all of the ways to get LO voltage at the output. Is that correct?

I found the following minterms which produce HI voltage or logical 1 at OUT, but am unsure how to make the K-map for 7 variables to simplify, so I'm working right now on using Boolean identities to simplify the logical function. (I couldn't figure out how to post the Excel spreadsheet with all 128 minterms). Basically, I would like to know if my approach is sound or if there is a shortcut method to get the logical function for OUT.

OUT

= A’B’C’D’E’F’G’+A’B’C’D’E’F’G +A’B’C’D’E’FG’ +A’B’C’D’E’FG

+ A’B’C’D’EF’G’ +A’B’C’D’EF’G +A’B’C’D’EFG’ +A’B’C’DE’F’G’

+A’B’C’DE’F’G +A’B’C’DE’FG’ +A’B’C’DE’FG +A’B’C’DEF’G’

+A’B’C’DEF’G +A’B’C’DEFG’ +A’B’CD’E’F’G’ +A’B’CD’E’F’G

+A’B’CD’E’FG’ +A’B’CD’E’FG +A’B’CD’EF’G’ +A’B’CD’EF’G

+A’B’CD’EFG’ +A’B’CDE’F’G’ +A’B’CDE’F’G +A’B’CDE’FG’

+A’B’CDE’FG +A’BC’D’E’F’G’ +A’BC’D’E’F’G +A’BC’D’E’FG’

+A’BC’D’EF’G’ +A’BC’D’EF’G +A’BC’D’EFG’ +A’BC’DE’F’G’

+A’BC’DE’F’G +A’BC’DE’FG’ +A’BC’DEF’G’ +A’BC’DEF’G

+A’BC’DEFG’ +A’BCD’E’F’G’ +A’BCD’E’F’G +A’BCD’E’FG’

+A’BCD’EF’G’ +A’BCD’EF’G +A’BCD’EFG’ +AB’C’D’E’F’G’

+AB'C'D'E'F'G +AB’C’D’E’FG’ +AB’C’D’E’FG +AB’C’D’EF’G’

+AB’C’D’EF’G +AB’C’D’EFG’ +AB’C’DE’F’G’ +AB’C’DE’F’G

+AB’C’DE’FG’+AB’C’DE’FG +AB’C’DEF’G’ +AB’C’DEF’G

+AB’C’DEFG’ +AB’CD’E’F’G’ +AB’CD’E’F’G +AB’CD’E’FG’

+AB’CD’E’FG +AB’CDE’F’G’ +AB’CDE’F’G +AB’CDE’FG’

+AB’CDE’FG +ABC’D’E’F’G’ +ABC’D’E’F’G +ABC’D’E’FG’

+ABC’D’EF’G’+ABC’D’EF’G +ABC’D’EFG’ +ABC’DE’F’G’

+ABC’DE’F’G +ABC’DE’FG’ +ABC’DEF’G’ +ABC’DEF’G

+ABC’DEFG’

Thanks, and I appreciate the advice.

Last edited: Sep 8, 2015
2. ### MikeML AAC Fanatic!

Oct 2, 2009
5,450
1,066
If you know all of the conditions that create a low (and I dont think you spotted all of them), isn't the complement of that expression all of the cases that create a high?

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3. ### WBahn Moderator

Mar 31, 2012
17,788
4,808
There's NO WAY I'm going to sift through all that!

The better way is to build up your logic function incrementally.

For example, notice that for OUT to be LO, either B or E must be HI. So that means

(OUT)' = (B+E)(something else)

Now break down the rest of the circuit below the B and E switches into similar portions that can be either OR'ed or AND'ed together. Once you are done, you have the Boolean expression for (OUT)' and you just need to NOT the entire thing to get the expression for OUT.

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4. ### J_Rod Thread Starter Member

Nov 4, 2014
109
6
Yes, I would have all of the minterms for each LO at OUT, and then multiply them together, and then logically NOT the expression. Is that what WBahn is suggesting, except using maxterms?

5. ### WBahn Moderator

Mar 31, 2012
17,788
4,808
No, I'm suggesting to get a much tamer Boolean expression direct from the topology. Remember, if two paths are in parallel, that is an OR relationship, while if two paths are in series, that is an AND relationship.

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6. ### J_Rod Thread Starter Member

Nov 4, 2014
109
6
I would follow each possible circuit connection, so

(OUT)' = (B +E)(FG +C(A +D)) = (B +E)(FG +AC +CD) = BFG +ABC +BCD +EFG +ACE +CDE
OUT = ((B +E)(FG +C(A +D)))'

I can check this with the truth table. Much simpler!

Last edited: Sep 8, 2015
7. ### WBahn Moderator

Mar 31, 2012
17,788
4,808
Now you're cookin'!

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