Logical Design question

Thread Starter

JerryNa

Joined Feb 15, 2010
32
Hello,
I'd appreciate your help with approaching this design question, faced in an interview:

Plan a logical design which gets a single read/write bit every clock cycle, and a number.
The design should store the histogram of the written input, and display it on a read command


What is the number's duty?

What does the system do when it gets read/write bit?


Is it that when it gets a read bit, it ignores the number and presents previous data,

And when it gets a write bit, it stores the number?
 

MrChips

Joined Oct 2, 2009
30,808
There is a single control signal called read/write.
There is an m-bit address bus called number.
What is missing is an n-bit data bus.

When the read/write control signal asserts a write command the m-bit address presents a memory address. The contents at that memory location is incremented by one.

When the read/write control signal asserts a read command the contents at the memory location at the m-bit address is read out to the n-bit data bus.

This is a typical pulse-height analyzer system in nuclear radiation spectroscopy.
 

Thread Starter

JerryNa

Joined Feb 15, 2010
32
There is a single control signal called read/write.
There is an m-bit address bus called number.
What is missing is an n-bit data bus.

When the read/write control signal asserts a write command the m-bit address presents a memory address. The contents at that memory location is incremented by one.

When the read/write control signal asserts a read command the contents at the memory location at the m-bit address is read out to the n-bit data bus.

This is a typical pulse-height analyzer system in nuclear radiation spectroscopy.

Hi Mr Chips,

Thank you very much!

I'm struggling with an issue.

The system gets every clock a read/write bit.

When the system gets a write command, it needs to perform both reading and writing in just one cycle:

1. Read address's content
2. increment content
3. write content to address

How do you design such system that does 2 memory actions (read then write) in one cycle?

How would you design the system with just one bus for both writing and reading?
 
Last edited:

Danm1

Joined Jul 19, 2010
69
since this is an interview question, then realize there is some leeway as to how you would answer it. It's very rare that they allow "take home" questions for the purposes of an interview, you just need to throw something at them. ;)

You can ask the forum for a solution to this weakly defined question, or you can just focus on preparing better for the next interview. Most times in an interview, you will do best to just be prepared to talk about some interesting project you designed or worked on.

Answering white board questions is a matter of maintaining your composure, even if you have no idea what they just asked.
 

Thread Starter

JerryNa

Joined Feb 15, 2010
32
Hi,
Thank you for your feedback.

I'm practicing this area of discrete systems, and I've been struggling with solving that one.

I don't know what's the area of the job being offered, i'm looking for Real-Time programming position, but since I have just 1-2 years experience, they may ask me questions like they ask one who just graduated.

My main issue2 here are two, and I'd appreciate it if you could advise on that:
- how do you conceptually perform the "Read -> Then Write" operation in one cycle?
- how do you make the data bus bi-directional?

Thank you very much for your time.
 

MrChips

Joined Oct 2, 2009
30,808
Hi,
- how do you conceptually perform the "Read -> Then Write" operation in one cycle?
Depends on your definition of a cycle.
Most computer systems can perform a read/modify/write operation.
A cycle can be broken down into smaller cycle steps internally in order to perform such operations.
- how do you make the data bus bi-directional?
Bi-directional buses are usually implemented with the use of tri-state bus drivers or bus transceivers that have tri-state capabilities.
 

Danm1

Joined Jul 19, 2010
69
If you are answering a hypothetical question about the read then write, I would say perform the read on the falling edge of the clock then the write in the rising edge, which gives half a clock cycle for signals to settle. You could also reverse it.
 

Thread Starter

JerryNa

Joined Feb 15, 2010
32
hi guys,

I've sketched the system.

I don't manage to translate it into Flip-Flops / Counters / Mux / etc.

The memory is given as a black box, but the rest needs to be translated to synchronized modules as FFs/ CNTR / Mux.

Could you please share your suggestion?

Thank you.

 

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MrChips

Joined Oct 2, 2009
30,808
It depends on what are your objectives.

Is this a question asked at a job interview?
Is this a hypothetical question?
Or is this a design for an actual application? If so, what is the application?
 

Thread Starter

JerryNa

Joined Feb 15, 2010
32
Hi Mr Chips,

This is a question from a job interview which i'm trying to solve.

It is very important for me to understand it, and i've been working on it for several days but did not manage to continue from that design.
 

MrChips

Joined Oct 2, 2009
30,808
So if this is an interview question, it is a hypothetical one.

The interviewer is not looking for actual implementation solutions but is testing your ability to problem solve and conceptualize.

Here is my answer:




Notice the difference between your solution and mine.
Mine is simple (only two building blocks) and easy to follow.
 

Thread Starter

JerryNa

Joined Feb 15, 2010
32
Thank you Mr. Chips.

Would you suggest for the memory to have Output Enable pin so when it is read, Output is enabled, and when written, output is disabled.
 
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