On Page#76 in the Tektronix manual oscilloscope 2467
http://exodus.poly.edu/~kurt/manuals/manuals/Tektronix/TEK 2467B Operator.pdf

They are measuring the logic setup and Hold time. I'm not sure what a logic setup or hold time is , is it only for logic clock signals? and how do you measure the setup time and hold time?

 

How about going out and reading some of the material easily found on the internet about logic setup and hold times and try to answer your questions for yourself for a change. Do that first, then come back and describe what you have learned and ask about specific details that you are still unclear on.

 

That's not the way the tolls roll.

 

Setup time
the interval "Before" the clock edge/event where the data must be held stable & sampled
hold Time-
the interval "After" the clock edge/event where the data much be held stable

I don't understand what is a Positive hold time and a Negative hold Time

Do you only measure the setup time and hold time whenever you see a flip flop on a schematic? or when do you measure the setup time and hold time? when would a test technician measure the setup time and hold time?

Yes i know the setup time and hold time is compared from a clock signal to a data signal but is it only for flip flops or what else?

When have you guys measured the setup time and hold time in a circuit?

Measuring the setup time and hold time
Ch1 is the clock signal
Ch2 is the data signal

To measure the setup time, you measure the data signal falling edge to the clocks leading edge?
To measure the holdup time, you measure the clocks falling edge to the data signals falling edge?

 

I don't understand what is a Positive hold time and a Negative hold Time

What have you done to try to figure it out (other than asking others to explain it to you)?

If Setup Time is the interval before the event edge where data must be stable by, then a +10ns setup time means that the data must be stable no later than 10ns before the sensitive edge of the event. If the setup time is -10ns, then this means that the data must be stable no later than -10ns before the sensitive edge of the event. Well, what is another way of saying -10ns before the sensitive edge?

Do you only measure the setup time and hold time whenever you see a flip flop on a schematic? or when do you measure the setup time and hold time? when would a test technician measure the setup time and hold time?
Yes i know the setup time and hold time is compared from a clock signal to a data signal but is it only for flip flops or what else?

Flip flops are the most common place where setup/hold times come into play, but any time you are sampling a signal for any reason also qualifies.

When have you guys measured the setup time and hold time in a circuit?

When I wanted a design that was pushing the limits to work or when trying to figure out why a design that was pushing the limits wasn't working.

Measuring the setup time and hold time
Ch1 is the clock signal
Ch2 is the data signal

To measure the setup time, you measure the data signal falling edge to the clocks leading edge?
To measure the holdup time, you measure the clocks falling edge to the data signals falling edge?

Why are you only looking at the specific edges you mention?

 

Flip flops are the most common place where setup/hold times come into play, but any time you are sampling a signal for any reason also qualifies.

What else have you measured as in a circuit or logic component to measure the set up time and hold time for besides a flip flop?

If the setup time is -10ns, then this means that the data must be stable no later than -10ns before the sensitive edge of the event.

This is the hold time when it's -10ns ? I still don't understand what is -negative hold time

a +10ns setup time means that the data must be stable no later than 10ns before the sensitive edge of the event. If the setup time is -10ns, then this means that the data must be stable no later than -10ns before the sensitive edge of the event.

This doesn't make sense, how can you have -10nSec before the leading edge of the clock
I do understand you can have +10nSeconds before the leading edge of the clock, but how can you have -10nSec before the leading edge of the clock?

I still don't understand what is negative set up time and negative hold time

 

When have you guys measured the setup time and hold time in a circuit?

I do this every time I need to design, test and verify a circuit for correct operation if I need the circuit to function reliably.

 

Mr.chips where do you get the setup times and hold times, do u just print out every datasheet for each logic Ic chip to make sure the setup time and hold time are measured to the datasheets of each IC chip? the data sheets tell the setup time and hold for flip flops and registers

 

You have it wrong.

Setup and hold times are not properties of a chip for you to measure. It is a requirement for you to comply with if you want reliable operation.

You read the manufacturer's datasheet and make sure your design satisfies those specifications.

Then you measure the behavior of YOUR CIRCUIT (not the manufactured chips) on the oscilloscope to verify that those specifications are met.

 

So how do you know if you have the correct setup times and hold times? you have to adjust the clock signal and input data signals and put delay networks in the "path" of the clock signal and delay networks in the "path" of the data signals so you get the correct setup times and hold times for each stage?

Only Flips flops and Registers had setup times and hold times? anything else?

 

Microprocessors, microcontrollers, memory, UART, I2C, SPI, ADC, DAC, LCD, etc., etc.

 

So how do you know if you have the correct setup times and hold times?

1: Read data sheet.
B: Design circuit to respect limits of the data sheet.
III: Build circuit then measure actual signals.
4: Compare measurements to data sheet limits.

 

Flip flops are the most common place where setup/hold times come into play, but any time you are sampling a signal for any reason also qualifies.

What else have you measured as in a circuit or logic component to measure the set up time and hold time for besides a flip flop?

If the setup time is -10ns, then this means that the data must be stable no later than -10ns before the sensitive edge of the event.

This is the hold time when it's -10ns ? I still don't understand what is -negative hold time

a +10ns setup time means that the data must be stable no later than 10ns before the sensitive edge of the event. If the setup time is -10ns, then this means that the data must be stable no later than -10ns before the sensitive edge of the event.

This doesn't make sense, how can you have -10nSec before the leading edge of the clock
I do understand you can have +10nSeconds before the leading edge of the clock, but how can you have -10nSec before the leading edge of the clock?

I still don't understand what is negative set up time and negative hold time

If I tell you that the elevation of Badwater, CA is -282 ft above sea level, what does that mean?

 

I'm guessing u need to place delay networks in the path of the data signal and clock signal to adjust and get the correct timing for the setup time and hold time? how does a designer get the setup time and hold time for each flip flop or register?

 

I'm guessing u need to place delay networks in the path of the data signal and clock signal to adjust and get the correct timing for the setup time and hold time?

That's generally a very poor way to go about designing a circuit, but there are times when things like that are done.

how does a designer get the setup time and hold time for each flip flop or register?

From the data sheet for the flip flop or register. Or from direct measurement and/or simulation if that is not possible. Just a couple weeks ago I had to determine the set-up and hold-time requirements for a DFF via simulation because we had never implemented it in the technology we were going to be using for that project.

 

The data signal and clock signal have to be "offset in time or out of sync" to get a setup time and hold time. If the Data signal and clock signal are aligned and in-sync you won't have a setup time and hold time?

If the Data signal and clock signal are aligned and in-sync , how do you design it to have a setup time and hold time?

 

The data signal and clock signal have to be "offset in time or out of sync" to get a setup time and hold time. If the Data signal and clock signal are aligned and in-sync you won't have a setup time and hold time?

If the Data signal and clock signal are aligned and in-sync , how do you design it to have a setup time and hold time?

It's pretty clear that you do not comprehend what setup and hold times are conceptually, despite all that has been said.

In your own words, if you had to describe what setup and hold times are to someone that has never heard of the concept before, what would you tell them?

 

Setup time is the time duration of the Data signal that is BEFORE the clock signal leading edge
Hold time is the time duration of the data signal that is AFTER the clock signals leading edge

If the Data signal leading edge and Clock signals leading edge are aligned and locked in-sync , you will have no setup time or hold time

 

Setup time is the time duration of the Data signal that is BEFORE the clock signal leading edge
Hold time is the time duration of the data signal that is AFTER the clock signals leading edge

Those aren't in your own words, you are just regurgitating what you regurgitated earlier.
What is the purpose of the setup and hold times? What does it accomplish? What happens if they are not met?

If the Data signal leading edge and Clock signals leading edge are aligned and locked in-sync , you will have no setup time or hold time

That's rubbish. The setup and hold times do not magically vanish if the data signal and clock signals are aligned. Setup and hold times are properties of the device being used. Signals can be locked in-sync and still violate setup and hold requirements.

 

What is the purpose of the setup and hold times?

To capture a sample of the data signal

What does it accomplish?

To store the data signal

What happens if they are not met?

The Flip flop won't sample or store the data signal

Setup and hold times are properties of the device being used. Signals can be locked in-sync and still violate setup and hold requirements.

True, but the data signals and clock signal need to be "offset between each other in time" so the setup time interval for the data signal is BEFORE the clocks leading edge.

There is an input capacitor inside the Logic Ic chip , flip flop that needs to be charged, so it needs a "setup time" for it to change/rise time so it can sample/store the data signal

The Clock signal just enables turns on the sample/store time