Hi,

I have truth table for some logic for which im trying to minimize. the smallest i can get it is 4 7 input and gates however im trying to look for patterns to see if i can get it any smaller .

Any help with minimizing the logic without such large input gates would be great.

 

That output is the LSB of a priority encoder. I don't think it gets any smaller

 

How about 2 4-input gates, and 3 3-input gates, plus 3 two input gates

 

How about 6 - 2 input gates?

 

Hi,

I have truth table for some logic for which im trying to minimize. the smallest i can get it is 4 7 input and gates however im trying to look for patterns to see if i can get it any smaller .

Any help with minimizing the logic without such large input gates would be great.

View attachment 84075

What is the output for the other 120 possible combinations? Are they LO or are they Don't Care?

 

One chip, or eight 2-input gates. Parity Generator:

http://www.datasheetarchive.com/dlmain/Datasheets-112/DSAP0046473.pdf

http://picprojects.org/projects/images/Paritygen.png

ak

 

One chip, or eight 2-input gates. Parity Generator:

http://www.datasheetarchive.com/dlmain/Datasheets-112/DSAP0046473.pdf

http://picprojects.org/projects/images/Paritygen.png

ak

If a parity generator is sufficient (which is not known since we don't know what the requirements are for the other 120 possible combinations), then only six 2-input gates are needed since there are only seven bits. Even if there were eight bits it would only require seven, though much better performance can be had with eight.