Logic paterns

Discussion in 'The Projects Forum' started by Mark_varney, Apr 15, 2015.

  1. Mark_varney

    Thread Starter New Member

    Dec 1, 2013
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    0
    Hi,

    I have truth table for some logic for which im trying to minimize. the smallest i can get it is 4 7 input and gates however im trying to look for patterns to see if i can get it any smaller .

    Any help with minimizing the logic without such large input gates would be great.

    truth table.png
     
  2. JWHassler

    Member

    Sep 25, 2013
    201
    33
    That output is the LSB of a priority encoder. I don't think it gets any smaller
     
  3. Papabravo

    Expert

    Feb 24, 2006
    10,145
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    How about 2 4-input gates, and 3 3-input gates, plus 3 two input gates
     
  4. djsfantasi

    AAC Fanatic!

    Apr 11, 2010
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    How about 6 - 2 input gates?
     
  5. WBahn

    Moderator

    Mar 31, 2012
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    What is the output for the other 120 possible combinations? Are they LO or are they Don't Care?
     
    djsfantasi likes this.
  6. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    Last edited: Apr 16, 2015
  7. WBahn

    Moderator

    Mar 31, 2012
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    If a parity generator is sufficient (which is not known since we don't know what the requirements are for the other 120 possible combinations), then only six 2-input gates are needed since there are only seven bits. Even if there were eight bits it would only require seven, though much better performance can be had with eight.
     
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