# Logic help.

Discussion in 'General Electronics Chat' started by bushrat, Jan 3, 2015.

1. ### bushrat Thread Starter Member

Nov 29, 2014
97
22
Hello Everyone,

I'm trying to work on my old project that I mostly forgot about. Most of it is almost done with exception of one small logic problem. I can't figure out how to complete it.

I have two inputs and one output.

Code (Text):
1. A    B    Y
2. 0    0    0
3. 1    0    0
4. 1    1    1
5. 1    0    1
6.
7. Repeats from here.
What gate combination can I use to achieve this output? No timing clock in this circuit, so some latches cannot be used.

2. ### #12 Expert

Nov 30, 2010
16,265
6,777
Looks like a "fail" from here.
1+0 = 0 and 1+0 = 1

3. ### MrChips Moderator

Oct 2, 2009
12,436
3,360
Your truth table shows an error/omission.

Look over your table and correct the error.

4. ### bushrat Thread Starter Member

Nov 29, 2014
97
22
No, not fail. That's the problem that I am having.

A is 1 volt, B is 5 volts.
Signal is voltage of capacitor charging.
When voltage is below 1 V, A and B are off. Output should be 0. (Charging capacitor)
When voltage is above 1 V, A is on and B is off. output should be 0. (Charging capacitor)
When voltage is above 5 V, A is on and B is on Output should be 1 (resets a charging circuit and starts discharging).
When voltage goes below 5 volts but above 1 volt, A is still on but B is off. Output should be 1 (Still discharging capacitor).
When voltage goes below 1 V, A is off and B is still off. Output should be 0 (starts charging capacitor again)

5. ### ian field Distinguished Member

Oct 27, 2012
4,413
782
Apart from the error in the truth table, it reminds me of gray code - but that's a method of counting that only one bit changes at a time.

6. ### MrChips Moderator

Oct 2, 2009
12,436
3,360
If you are attempting to describe a sequence of events then you will need a sequential circuit.
Try a flip-flop with reset and clear inputs, for example.

7. ### #12 Expert

Nov 30, 2010
16,265
6,777
You tried to describe an analog sequence in digital terms. In analog, this can be done with hysteresis. One op-amp can do this.

8. ### cmartinez AAC Fanatic!

Jan 17, 2007
3,567
2,532
You have to use a latch, or some form of memory that stores previous states, since what you've stated is not a logic table, but series of results that depend on past entries

9. ### cmartinez AAC Fanatic!

Jan 17, 2007
3,567
2,532
Here's your circuit, I've already tested it in Digital Works, and it seems to work just fine

bushrat and #12 like this.
10. ### cmartinez AAC Fanatic!

Jan 17, 2007
3,567
2,532
And here's the simulation, shown step by step:

11. ### bushrat Thread Starter Member

Nov 29, 2014
97
22

Thank You. I will try it our today..

12. ### bushrat Thread Starter Member

Nov 29, 2014
97
22
Sorry for late reply, got distracted with other things..
Works perfect, Thank you cmartinez..

13. ### WBahn Moderator

Mar 31, 2012
17,726
4,788
Asynchronous designs are intrinsically risky and what happens in the case of race conditions or glitching needs to be considered carefully.

In this case the glitching (possibly severe) when comparator B transitions shouldn't have an effect because it doesn't matter if we latch in the current value of A on either edge of B. If the design was such that A could go LO before B does and we are relying on nothing happening when B goes LO (i.e., the falling edge of the clock) then this circuit would almost certainly fail even though it might look good on paper and work as desired in a simulator.

Similarly, the glitching (possibly severe) when comparator A transitions shouldn't have an effect because at either transition point we want the output to be LO and so we don't care if it gets reset multiple times.

So this design should work in the real world.

But a better approach would probably still be to use a Schmitt trigger comparator (as #12 said, this can be done with a single opamp) with thresholds set to 1V and 4V.

14. ### cmartinez AAC Fanatic!

Jan 17, 2007
3,567
2,532
Yeah, I know what you mean... I was going to suggest adding caps to the design so as to smooth transition between the gates and absorb possible glitches, as you say. But I got wrist slapped by a moderator in a previous post for giving away answers too easily... so I decided to keep my mouth shut this time... see what happened...