Logic Glitches...

Discussion in 'The Projects Forum' started by Enliten, Feb 18, 2009.

  1. Enliten

    Thread Starter Member

    Feb 10, 2009
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    I was debugging a circuit that seems to be down to logic glitches, having mainly been based in software and pure logic theory, the idea of these glitches was new to me. I understand that you can get short pulses of unwanted values, i.e. an ouput that was 1 might go to 0 then back to 1 when an input value changes - even though logically it should not become a 0.

    Can anyone explain this in a little more detail or put me onto a book/website with more info. I understand i can use a secondary flip flop to buffer these changes, but i would like to understand a bit more about where and why they appear and when i should be looking to buffer them.

    I presume it just the small delays in timings going through chips and mainly its clock pulses and flip flop pulses that need to be buffered in some way to protect them?

    Adrian
     
  2. eblc1388

    Senior Member

    Nov 28, 2008
    1,542
    102
    All I know about glitches is that they are not the fault of the logic circuit but due to signals arriving to its inputs with slight time delay between them.

    The logic gate is doing its best to tell you there is slight timing difference between the signals by producing a short but valid output that exactly 100% represent the state of the input. But often this is not one wanted so it is termed "glitch".

    So the logic circuit is not at fault here.

    If you try to decode a certain value N from various output stages of a ripple counter, you will get glitch because not all output stages changes at once.
     
  3. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    Post your circuit to clear things up.
     
  4. Enliten

    Thread Starter Member

    Feb 10, 2009
    17
    0
    Ill draw it up and post it this evening - Thanks
     
  5. Enliten

    Thread Starter Member

    Feb 10, 2009
    17
    0
    Attached is the basic drwaing of the circuit. It doesnt show all the +5/0V. Chips where terminals are not used are connected to 0v or 5v as needed. Also the comp. chips (74HC688) are hardwired to compare with the value shown in the =. Hope it makes sense, i really should find a free program to design these ;). But this usually serves me for building the system.

    I was speaking to someone who has done a similar- yet alot more complex circuit and he says i really need to add a buffer between the comp. chips and the D Flip flop - as its the comp. that can give glitches while the comparison lines settle from the counter chip.
     
  6. mik3

    Senior Member

    Feb 4, 2008
    4,846
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    The glitches happen because the outputs of the counter are not changing simultaneously. Also, because you are using a ripple counter the situation gets very worse.
     
  7. Enliten

    Thread Starter Member

    Feb 10, 2009
    17
    0
    I am going to put a 574 flipflop to buffer the glitches from the comp. 688 chips as per someones recommendation. What would you suggest instead of ripple counters?
     
  8. Enliten

    Thread Starter Member

    Feb 10, 2009
    17
    0
    I was reading up on the ripple counters, in this situation the ripple is fine as im mainly using it as a clock divider, so it doesnt matter too much about the ripple effect, but ill certainly keep it in mind :D
     
  9. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    Even if the 8 bit counter is not a ripple one its outputs won't change simultaneously because nothing is perfect.

    You can use a D flip flop on the output of each comparator which will trigger at the negative edge of the clock signal which drives the 8 bit counter. Also, the 8 bit counter has to increment on each positive edge of its clock signal.

    In this way the outputs of the counter will change on the positive edge and they will try to settle down to their final value. During this time the flip flops output won't change until a negative edge (from the clock signal of the 8 bit counter) triggers them.

    You have to ensure that the outputs of the counter will settle down before the negative edge of the clock triggers the flip flops.
     
  10. Enliten

    Thread Starter Member

    Feb 10, 2009
    17
    0
    Thanks for your suggestions. Ive reworked the circuit to include a D Flipflop buffer of the comparitors and clocked them via an inverted clock pulse used on the RCK of the 8bit counter.

    I just need to build up the VSYNC section and hopefully this circuit will happily generate a 640x480@60Hz vga signal :)

    Adrian
     
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