# Logic gates minimization

Discussion in 'General Electronics Chat' started by Dritech, Feb 15, 2013.

1. ### Dritech Thread Starter Well-Known Member

Sep 21, 2011
756
5
Hi all,

From the attached schematic diagram, how can I do a NAND gates minimization?

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2. ### tshuck Well-Known Member

Oct 18, 2012
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Looks like you cut a couple minterms from the bottom there

No worries...

The easiest way would probably utilize DeMorgan's theorem in order to make the minterms into all NAND implimentations.

You could also attempt to redraw the circuit with NANDs and try to reduce that way.

3. ### Dritech Thread Starter Well-Known Member

Sep 21, 2011
756
5
Hi tshuck,

I managed to do the NAND gate minimization, but is there a way to simplify the circuit (the one attached) ??

(by the way, the photo shows a part of the circuit)

Thanks.

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4. ### Dritech Thread Starter Well-Known Member

Sep 21, 2011
756
5
Any help please? I tried using boolean algebra but I did not manage to minimize it while leaving all gates as NANDs.

5. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
If you did the work, post it....

Also, your transformation to an all NAND implementation is wrong.

See here
specifically, this:

6. ### kubeek AAC Fanatic!

Sep 20, 2005
4,687
805
You should start by getting some minimal form of the input, and then translate the logic functions to gates. Also check if your requirement asks specifically for 2-input nand gates, that complicates things a little more.

7. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
Hint: You have to be comfortable with DeMorgan's Theorem to work the Boolean magic....