Why does logic circuits get damaged really fast when the +VCC drops?

Lowering the +VCC voltage on a transistor or mosfet doesn't damage it. But TTL chips and CMOS chips get damaged or heat up fast when lowering the +VCC. Any reasons why?

The propagation delay gets worse when you lower the +VCC , any reasons why?

 

What's PCB?
Which number of IC, schematic or brand, type or model?
Please attach photos.

 

Logic chips can go into an abnormal mode when operating below their rated voltage and that can cause excessive current draw and overheating.

Lowering the voltage also can lower the speed of the transistors, which increases propagation delay in the chip.

 

Why does logic circuits get damaged really fast when the +VCC drops?...

Succinctly, one or more of the following: latch-up, oscillation, heating corollary to 'quasi-saturation'...

Best regards
HP

 

Why does logic circuits get damaged really fast when the +VCC drops?

How fast is fast?

Lowering the +VCC voltage on a transistor or mosfet doesn't damage it. But TTL chips and CMOS chips get damaged or heat up fast when lowering the +VCC. Any reasons why?

How low is low and at what rate is it changing?

 

If a logic chip has a high or 1 on some inputs, and Vcc drops below that voltage level, this can drive current through what is called a substrate diode. Because this is a non-allowed condition, there is nothing in the chip to limit the current through these diodes. This is more of a problem for CMOS parts than old TTL parts, and is only one of several failure modes.

ak

 

As seems typical of the OP, he's full of questions but short on details...

If a logic chip has a high or 1 on some inputs, and Vcc drops below that voltage level, this can drive current through what is called a substrate diode.

They're more generally called input protection diodes. Substrate diodes imply a PWELL process. In an NWELL process, the VCC clamp wouldn't be on the substrate. And to complicate matters more, some devices (e.g. CD4049/4050) don't have clamp diodes to VCC. This allows them to be used as level shifters.

Because this is a non-allowed condition, there is nothing in the chip to limit the current through these diodes.

The metalization in the chip would "probably" give out under severe conditions. If it didn't, there might be enough current to trigger latch up.

But no one would reduce the supply voltage on a circuit and continue to drive from low impedance sources. Or would they???

 

Not on purpose, maybe, but multi-output power supplies and POL regulators have been known to fail, leaving some parts with active input signals but no power. Also, I agree with your comments, but my post was directed to the TS. If he were as familiar with process details as many of the regular contributors are, he wouldn't have been asking the question. I was writing at his level and didn't see the need to clog up the response with subtleties he cannot process. Short on details always is a detail.

ak

 

As seems typical of the OP, he's full of questions but short on details...
They're more generally called input protection diodes. Substrate diodes imply a PWELL process. In an NWELL process, the VCC clamp wouldn't be on the substrate. And to complicate matters more, some devices (e.g. CD4049/4050) don't have clamp diodes to VCC. This allows them to be used as level shifters.

Most CMOS chips have a parasitic SCR on the inputs. If Vdd collapses while an input is held high, it latches up and can destroy the chip.

The most common example is a C/R delay power on reset where a capacitor shunting a reset input is charged by a resistor from Vdd. At power down, Vdd collapses but the charge on the capacitor still presents a voltage at the reset pin, this can cause unpredictable operation, or destroyed chip next power up.

Any input connected to anything that could hold a charge needs to be clamped to Vdd with an external diode.

 

Most CMOS chips have a parasitic SCR on the inputs. If Vdd collapses while an input is held high, it latches up and can destroy the chip.

There are 4 layer diodes everywhere there's an NMOS device close to a PMOS device; that's a very common topology.

The most common example is a C/R delay power on reset where a capacitor shunting a reset input is charged by a resistor from Vdd. At power down, Vdd collapses but the charge on the capacitor still presents a voltage at the reset pin, this can cause unpredictable operation, or destroyed chip next power up.

The current would need to be in excess of 10mA to cause any damage and how it manifested itself would depend on how the PMOS devices were connected to the power rail. Latch up resistant parts claim they can tolerate 100mA.

 

There are 4 layer diodes everywhere there's an NMOS device close to a PMOS device; that's a very common topology.
The current would need to be in excess of 10mA to cause any damage and how it manifested itself would depend on how the PMOS devices were connected to the power rail. Latch up resistant parts claim they can tolerate 100mA.

It was certainly a problem with the original bog-standard 4000 series.

Someone I knew years back was building a model rocket launch console with CMOS chips - by and large he's a competant engineer, but he missed a power on reset clamp diode and it caused a chaos he couldn't figure out!

 

It was certainly a problem with the original bog-standard 4000 series.

It's pretty well understood now, but it's still a concern; especially with dimension scaling.