Logic circuit for power on and off

Discussion in 'Homework Help' started by tehoaislimau, Mar 28, 2012.

  1. tehoaislimau

    Thread Starter New Member

    Mar 20, 2012
    5
    0
    Hello
    Need some advise.
    I am designing a simple power supply enable circuit. Please see attached schematic.

    The On OFF switch would be logically "OR"ed together with a MCU GPIO.

    The initial state of the POWER_HOLD_GPO would be LOW.
    Once the ON switch is pushed, it will ENABLE the power regulator and also the MCU.
    From then, the POWER_HOLD_GPO would be configured as output HIGH.

    To turn off, when the switch is opened, it will drive the line LOW and the ON_OFF_SENSE GPIO (input) to the MCU will sense it and start the power down sequence and save criticial info. Once its done it will set POWER_HOLD_GPO low and it should shut off the power regulator.

    My problem is, if during the power off sequence (ON_OFF_SWITCH =L & POWER_HOLD_GPO =H) and the MCU is within the power down sequence, and the ON/OFF switch is suddenly closed quickly enough prior the POWER_HOLD_GPO going LOW, the POWER_REGULATOR would be remain enabled, however the MCU has thought it would been powered down.

    How do I avoid this state?

    Any thoughts
     
  2. panic mode

    Senior Member

    Oct 10, 2011
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  3. tehoaislimau

    Thread Starter New Member

    Mar 20, 2012
    5
    0
    Hi (Panic Mode)
    Thanks for your replies.
    I am sure sure how the power monitors can help in this case.
    I went through the specification, and it seems to be like voltage supervisiors.

    The problem that I am facing is that, in the condition that the MCU happens to be powering down, and suddenly the ON switch is closed, the output of the "OR" gate would remain HIGH, thus, POWER_ON output would also remain HIGH.
    This condition prevents the voltage regulators to remain turned on, but the MCU thinks its already off.... this causes battery drain.
     
  4. panic mode

    Senior Member

    Oct 10, 2011
    1,318
    304
    i see,

    maybe using interrupt on rising edge of that signal would fix it (wake up mcu if needed)?
     
  5. tehoaislimau

    Thread Starter New Member

    Mar 20, 2012
    5
    0
    Hi
    Yes, the backup plan to for my MCU to poll/interrupted by the ON_OFF_SENSE GPIO to stop the power down process.
    The only thing is, there still might be a small (but unlikely) window of opportunity for the state to occur.

    I am hoping that there is a logical fail safe way of preventing this from a logical point of view, maybe by using flip flops of more elaborate array of gates.

    I'm pretty sure this application is seen in many electronics products, and I wonder how they had overcome it.
     
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