Discussion in 'Homework Help' started by OMMad, Dec 20, 2010.

Nov 14, 2010
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homework help please. the assignment is to design a countdown timer that goes from 67 to 0 and back to 67. the output is two DCD_HEX displays.

what i've done is divide the circuit into two parts, one for the ones digit (4 bits) and the other is for the tens digit (3-bits). i then used truth tables and karnaugh maps to design each sub-circuit.

i need help designing a loadable counter because i want the ones digit display to start countdown from 7, but then proceed to loop normally (from 9 to 0). any links to online resources or direct help would be greatly appreciatred.

2. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
A standard IC counter does have the option of preloading. If you want to stick to a JK-FF implementation, they too, have Set and Reset buttons that can do the same job.

Care to explain a bit more how do you plan to recognize the limits of your counting and how you convert binary to decimal? Maybe we can find some other loopholes.

Nov 14, 2010
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well the only problem i'm having now is actually getting the loop to start at 7.

when using karnaugh maps to derive the excitation table i used this for the clock input:

7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 7

with the hope that the clock would begin at seven and loop around. naturally the excitation tables i got were exactly the same as a normal decimal loop so the countdown begins with 9.

i've considered placing AND gates that set/reset specific FLIP-FLOPS when the tens digit was 6 and the ones digit was 9 (thus defaulting the ones digit to 7 ONLY WHEN the tens digit was 6). would this be a viable solution?

4. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
In general you can do anything with enough Boolean circuits.

How do you plan to count down from 67? I suggest you take a look here first:

Study the "Up/Down Counter" a bit. After you understand its operation, you will see that you can control it with only 1 bit. You will need two 4-bit counters to implement the 2 digits. I will refer to the 4 JK-FFs that constitute the decades figure as df and to the other 4 as uf.

You will need circuits that will implement the following logic:
if D (direction) is 0 (up) then
if (df (decades figure) == 0110) and (uf (units figure) == 0111) then
D = 1
else if (uf == 1010) then reset uf
else if (df == 0000) and (uf == 0000) then
D = 0
else if (uf == 1111) then uf = 1001

The limits might need some tweaking in order to work properly. Of course you need an overflow bit from the uf to clock the df. Keep in mind that there's a different test for the count up and count down.

I admit it is somewhat complex, but it covers all possible options. If someone has a simpler solution, I 'd be glad to hear it.

You can form the expressions to be tested with Boolean expressions and you can branch the "ifs" with MUXs or AND gates.

Is that clear?
Can you start building some expressions and parts of the circuit?