Here is a power amplifier with load resistance, RT.
Does load impedance, RT, have anything to do with L1?
I mean that if load resistance depends on L1 or not. When writing its load line equation, which load I need to use, inductive impedance or RT?

 

What are you defining to be the "load" and what are you defining to be the "amplifier"?

Draw the small-signal equivalent circuit and I think things will be a lot clearer to you.

 

What are you defining to be the "load" and what are you defining to be the "amplifier"?

In my book, it is not specified clearly. If I am not mistaken, here is what the book want to tell.
The matching network is used to convert the load resistance, RL, to a lower value, RT. Therefore, the power deliveried to the load will increase.

The output power in two cases:

+ Without matching network:

\(P_{out} = \frac{V_{DD} ^{2} }{2 R_{L} } \)

+ With the presence of matching network:

\(P_{out} = \frac{V_{DD} ^{2} }{2 R_{T} } \)

Because of RT << RL , the output power will increase significantly.

The amplifier in this case is the NMOS transistor.

I am confused as reading this from another book.
In order to increase the linear output power, there are basically only two main steps that can be taken:

1. Increase the IQ(quiescent current): this would increase the Pout through RL reduction in order to keep the maximum swing of the output voltage constant.

2. Increase the VDD: although digital circuits tend to use the lowest VDD possible, this is not necessarily the case for analog circuits. Increasing the VDD will also reduce the impact of the VKNEE.

I don't understand #1.
a) As IQ increases, the transconductance of transistor gm also increases and therefore Pout increases.
b) If RL are reduced then Pout also increases.

But it seems to me that a and b have nothing to do with each other. And therefore, not what #1 meant.

 

Where are you getting that Pout is (Vdd)^2/(2RL)?

What kind of matching network are we talking about? Is it frequency selective?

 

It is clear that load resistance seen by the amplifier is L1||M*RL (I ignored MOS rds resistance)
Where M is a machining network factor. But in RF circuit we select XL1>>M*RL
So we left with M*RL

 

Where are you getting that Pout is (Vdd)^2/(2RL)?

I assume that the signals (voltage and current) at the load are sinusoidal signals. Let's say that the with peak voltage Vp and in the circuit above Vp is chosen to equal to VDD.

\(P_{out} = \frac{ V_{rms} ^{2} }{ R_{L} } = \frac{ (\frac{ V_{p } }{ \sqrt{2}})^{2} }{ R_{L} } = \frac{ V_{p} ^{2} }{2R_{L} }= P_{out} = \frac{ V_{rms} ^{2} }{ R_{L} } = \frac{ (\frac{ V_{p } }{ \sqrt{2}})^{2} }{ R_{L} } = \frac{ V_{p} ^{2} }{2R_{L} } = \frac{ V_{DD} ^{2} }{2R_{L} } \)

What kind of matching network are we talking about? Is it frequency selective?

I think so. They, maybe, are formed from L, C or transformer as this one.

 

It is clear that load resistance seen by the amplifier is L1||M*RL (I ignored MOS rds resistance)
Where M is a machining network factor. But in RF circuit we select XL1>>M*RL
So we left with M*RL

I see. Can you help me explain this?

In order to increase output power we can:
Increase the IQ(quiescent current): this would increase the Pout through RL reduction in order to keep the maximum swing of the output voltage constant.

I think this statement should be divided into two methods.
+ Increase the IQ(quiescent current)
+ Reduce load resistance, RL.

These two methods have nothing to do with each other. Is my understanding correct?

 

I think that the book statement is correct. Why? Think of a load line with constant RL.
So now if we increase quiescent current we shift "maximum swing". We have now more negative swing than positive one.

 

I assume that the signals (voltage and current) at the load are sinusoidal signals. Let's say that the with peak voltage Vp and in the circuit above Vp is chosen to equal to VDD.

But on what basis do you claim that you can choose Vp to be equal to Vdd? Why not "choose" it to be 10*Vdd? Surely there are limits on what you can choose Vp to be. How do you know that choosing Vp to be equal to Vdd does not violate those limits?

 

I think that the book statement is correct. Why? Think of a load line with constant RL.
So now if we increase quiescent current we shift "maximum swing". We have now more negative swing than positive one.

I don't really understand this. Do you mean that if we increase IQ and decrease RL simultaneously then the voltage swing at drain is unchanged and we sitll have symmetrical signal?
I don't know why RL is related to Id-Vds of mosfet. I think the load line in this case have to write with the load of inductor ωL.

But on what basis do you claim that you can choose Vp to be equal to Vdd? Why not "choose" it to be 10*Vdd? Surely there are limits on what you can choose Vp to be. How do you know that choosing Vp to be equal to Vdd does not violate those limits?

The voltage at drain in DC mode is VDD. As my understanding, the maximum symmetrical RF signal swing at drain will be 2VDD. It ranges from 0 to 2VDD.