# Linear regulated power supply design help

Discussion in 'General Electronics Chat' started by PaulEE, Aug 30, 2014.

1. ### PaulEE Thread Starter Member

Dec 23, 2011
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Hello all,

I am trying to design a linear regulator (no LM317, no uA723, ...opamps, resistors, diodes, etc.).

The goal is to achieve 0 - 30VDC at 0 - 3ADC. I would like to regulate both voltage and current, and would like the current-limiting to "kick-in" when the load under power draws more "than it should".

Example: 10 V on load of 10 ohms draws 1 amp. If the current setpoint is 2 ADC, all is well. If I then feed 20 VDC without changing the current setpoint, I would like current to be pegged at 1 ADC.

What I have so far is the usual Vref into +Vin on an opamp and I have the -Vin coming from the top of the load back to the opamp. Opamp drives transistor, transistor drives load. This works great. In my actual circuit, the voltage is measured differentially across the load and fed back because of the current sense resistor just below it...

I then (again, differentially) "read the current" via the shunt resistor and another amplifier. Here's where I'm stumped...what design/topology/technique should I employ such that a breach in the current limit pulls the voltage setpoint down until there is no more breach? I've tried a ton of ideas on SPICE, keeping in mind real-world tolerances and issues. I just can't seem to get to the correct solution. It almost seems like I need to dynamically calculate the load resistance in order to determine the associated voltage setpoint change, but I refuse to believe this is the straightforward method.

Any help or guidance would be appreciated!

2. ### #12 Expert

Nov 30, 2010
16,665
7,310
You seem to have contradicted yourself.
That said, a constant current regulator will pull the applied voltage down to exactly the current limit you asked for.
The 723 chip has a foldback circuit that will collapse the voltage if the current gets too high.
It seems a shame to refuse to use modern chips because they work very well and the associated circuitry is simpler.

Shall I continue?

3. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
I am asking how to implement this using op-amps and other discrete components because the eventual resolution of the control of the outputs will be more than what the uA723 was intended for...and because I'd like to know

4. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
Perhaps I should re-phrase...

I built a linear regulator in which voltage is very tightly-controlled and the voltage and currents on and through the load are very accurately known. Using these values available, what is the best way, or what are several popular ways, to implement current limiting when the current setpoint is passed due to decreased load impedance?

5. ### #12 Expert

Nov 30, 2010
16,665
7,310
This is a basic, one transistor constant current limiter. It can be much more precise with an op-amp.

What quality of resolution are you looking for?

ps, this will get a lot easier if you post the circuit you're working with.

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6. ### PaulEE Thread Starter Member

Dec 23, 2011
423
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I'm looking for 1 mA resolution. The current sense resistor in this circuit is 0.1 ohms +/- 10 ppm (it is a custom wire-wound part with low TC wire)

7. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
The challenge for me isn't so much the current limiting - the challenge for me is to figure out how to implement it seamlessly and continuously with the circuit described. Am I making sense? And thank you for the replies-

8. ### #12 Expert

Nov 30, 2010
16,665
7,310
100 uvolts locks the current at .9990 amps to 1.001 amps?

Hang on. .1 ohm at 1 amp is 100 mv.
Having difficulty with math this week.

9. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
1 volt/amp is how I scaled the reading. See attached...

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10. ### AncientNorm New Member

Aug 30, 2014
2
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You need a sort of analog OR gate. This can be as simple as pulling down (resistor to Vcc) drive to the pass transistor via diodes from the outputs of the op amps. The non-controlling op amp output will saturate towards the +ve rail.

11. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
Do you have an example schematic to illustrate this? I thought about using 4066 switches to switch between control signals, but this wasn't as elegant as what I'd imagined.

12. ### #12 Expert

Nov 30, 2010
16,665
7,310
Something like this?

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13. ### PaulEE Thread Starter Member

Dec 23, 2011
423
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Exactly! Except for some reason it didn't work when I simulated it, although, I had been driving a 2N4401 NPN transistor's base with your bottom current opamp to "pull down" the setpoint. And it wasn't working...but I will set it up in the way I've got it in my SPICE program and attempt it again. Perhaps the transistor wasn't the right thought process.

14. ### #12 Expert

Nov 30, 2010
16,665
7,310
I don't simulate. If you're having difficulty with SPICE, you're going out of my range.

15. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
Ah ha...the -Vin on the voltage controlling op-amp. Mine is getting an accurate voltage reading. Would I have to toggle between the current/voltage feedback controlling pins, or could I have them both hooked up in tandem? As of now I've not had much luck with the in-tandem technique...

16. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
I see. I usually don't either, but there are certain benefits. I plan to wire this up soon (like tonight on into the morning).

17. ### #12 Expert

Nov 30, 2010
16,665
7,310
That concept I drew will sit there obeying the voltage command until the current limit is hit. Then the lower op-amp will pull the voltage command down to maintain the current you set. So, tandem = yes.

18. ### PaulEE Thread Starter Member

Dec 23, 2011
423
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My thoughts exactly, which was why I was getting discouraged with the simulation results. Perhaps I really should go back to my old ways of real-life simulation. At what point (if there was one) did you decide SPICE was useless? (or any variation in between)?

19. ### #12 Expert

Nov 30, 2010
16,665
7,310
I tried to run a simulation of a jfet amplifier stage with op-amp controlled DC feedback to compensate for the natural variance in jfet IDSS ranges. I had to build it one component at a time or the simulator couldn't figure it out. After more than an hour of adding one or 2 components at a time, it finally worked. I thought a simulator should work better than that.

20. ### PaulEE Thread Starter Member

Dec 23, 2011
423
32
Well I tend to agree. I will be building this as soon as my steaks are done on the charcoal grill I will definitely keep everyone posted on the results. I appreciate the help, all.