linear region of MOS FET

Discussion in 'Homework Help' started by maheshg, Aug 11, 2010.

  1. maheshg

    Thread Starter New Member

    Aug 11, 2010
    6
    0
    How large Vds decreases vertical field component in NMOS FET?
     
  2. Ghar

    Active Member

    Mar 8, 2010
    655
    72
    (All comments apply to a lateral FET in an IC, not a vertical power FET)


    You have 4 terminals you're looking at:
    Gate
    Source
    Drain
    Bulk

    Usually the bulk is tied to 0. Let's say the source is also 0.
    Vb = 0
    Vs = 0

    To turn the NMOS on you apply a positive Vgs.
    That gives you:
    Vgs = Vg

    Notice that the FET is symmetrical though, the source and drain are the same thing.

    When you apply a Vd, you get:
    Vds = Vd

    Now, look at the gate to terminal voltages:

    Vgs = Vg
    Vgd = Vg - Vd

    Vgd is smaller than Vgs.
    Electric field is voltage / distance.
    The distances are equal from gate-to-source and gate-to-drain

    This gives you much weaker electric field between gate and drain than gate and source.
    This means the channel is larger at the source than at the drain.
     
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