Hi,

I have enclosed a file showing an 8-bit comparator. If we consider one of the numbers are predefined, I want to limit the number of times one can check the other to three times. It means that if after three times one entered the wrong number, the circuit gets locked and a buzzer starts.

Could anyone suggest how I can do it?

 

Hello sryzdn

Somehow we must "remember" how many attempts have been made. (A counter).

When it reaches 3, the same circuitry must inhibit the programming keys and the buzzer should sound.

You should also have a button to reset the system.

 

I would use the A>B and A<B outputs of the second comparator to step a 4017 counter.

When it reaches a count of 3 it would disable the 4017 from further counting until it is reset. At the same time it switches on the buzzer using a NPN transistor. Shouldnt be too hard for you to design it.

Allen

 

I would use the A>B and A<B outputs of the second comparator to step a 4017 counter.

When it reaches a count of 3 it would diable the 4017 from further counting until it is reset. At the same time it switches on the buzzer using a NPN transistor. Shouldnt be too hard for you to design it.

Allen

I followed you and added a 4017, however at this stage 4017 does not disable the circuit after three times and also the stepping of 4017 is not correct.

I really don't ask you guys to solve the whole problem for me. But as I am a VERY newbie, I need some suggestions to know where I should start.

 

Good, you're making progress.

When the 4017 is switched on, the output is usually in a random state. You should have a power-on-reset on the MR. Or put a button to pull it high to reset it before game starts.

When the 4017 is reset, Q0 becomes 'H' and the rest of the outputs are 'L'. So the first guess would step Q1 and second guess Q2. On the 3rd guess, Q3 is high and this high is sent to 'enable' pin of 4017 so any further input clocks are ignored.

Now comes the problem. Let's say your preset number is '10001000' and the guessed number is '01010101' and assumming the initial guess pattern is '00000000'. Every time the palyer change one bit of the guess pattern, it would generate one clock pulse. After entering '01010101', 4 clocks have been generated. The 3-trials limit would have expired before the player finished entering the first number.

So how are you going to tackle this problem? Give it some thoughts and come back with a solution.

Allen

 

Good, you're making progress.

When the 4017 is switched on, the output is usually in a random state. You should have a power-on-reset on the MR. Or put a button to pull it high to reset it before game starts.

When the 4017 is reset, Q0 becomes 'H' and the rest of the outputs are 'L'. So the first guess would step Q1 and second guess Q2. On the 3rd guess, Q3 is high and this high is sent to 'enable' pin of 4017 so any further input clocks are ignored.

I'm afraid I'm coming back with no good progress

I tried to simplify the circuit with a 4 bit comparator. It seems the button does not reset 4017 Q0 and also, it keeps turning on the diodes on random. Should I change the input of CLK?

Now comes the problem. Let's say your preset number is '10001000' and the guessed number is '01010101' and assumming the initial guess pattern is '00000000'. Every time the palyer change one bit of the guess pattern, it would generate one clock pulse. After entering '01010101', 4 clocks have been generated. The 3-trials limit would have expired before the player finished entering the first number.

So how are you going to tackle this problem? Give it some thoughts and come back with a solution.

I really don't know. But I thought of a decoder. Perhaps I should add an "enter key" every time four digits were arranged and well, four enter keys would mean the buzzer alarm?! (Still have not given it a deep thought)

I hope I'm not going too astray. Could you help me solve the problem of 4017?

 

The attached is the connection of the 4017. C1 and R1 is the power-up-reset for the 4017 to always starts up at Q0 when power is applied.

The reset button will reset the 4017 when it is locked at the 3rd trial.

You need to define another button called "GUESS". So that when the 8-bit number is completely entered, it would be pressed so the result could be checked.

You need to read this too -

http://www.wisc-online.com/objects/ViewObject.aspx?ID=DIG3703


Allen

 

Hello sryzdn

Well, as we can see it is not so easy.

Some notes trying to help:

if you intend to make your PCB circuit,
LOGICSTATE will have no location on the PCB. these are only for the task of simulating the circuit.

Let me assume that the three attempts always adjust, the LOGICSTATE, A greater than B,
The 4027 will NOT count +1.
The same would happen if we adjust the LOGICSTATE: A lower then B.
Yes, this could be solved by the "GUESS" button suggested by member absf.

 

You need to define another button called "GUESS". So that when the 8-bit number is completely entered, it would be pressed so the result could be checked.

Allen

Thanks so much for sending the final design for 4017.
For the "GUESS" switch, I have done sth as enclosed. I hope you will let me know where I am going wrong.

 

I dont quite understand your schematic.

Are you connecting the B0-B3 like a bus and use 4 buttons (as in 4PST switch)? Nop, the solution is much simpler than that. The "GUESS" button would be connected after the XOR gate.

Did you read the link that I sent you. It contains important info on how to set up your 7485 correctly. From that link you can see that the 3 inputs of the 7485 cannot be left NC or else your circuit will not work correctly. Check it out yourself.

Allen

 

Hello sryzdn

If we look at your original design we can see that, more or less, you know how to use the comparator 7485.
Except you left without defining a logic level for inputs A<B, A=B, A>B, In comparator to the left.
In the simulations we can not give a logical level (Proteus ISIS) and works.
So I strongly suggest you draw back your original design.
But as shown in Figure M 1.jpg.
Give A look at the other pictures: 4 M, & M 6

Now: always remember that LED’s require a current limiting resistor.
This resistance is calculated based on the electrical characteristics of the LED you're using and the bias voltage.
(Vcc - Vf) / If = Rx.
Where:
Vcc = bias voltage.
Vf = voltage drop across the LED’s terminals when it is crossed by a If current.
If = maximum rated current crossing the LED.
Rx = Value of current limiting resistor in Ohms.
In the simulation can be without them and works.

From your post #6 You remove a comparator.
What is the reason ?.
And add an exclusive OR gate whose inputs are connecting through few LED's.

The exclusive OR gate; I do not think that helps your design.
How it works?
Observe its logic symbol.
Its inputs, along with the curve on them, resembling the mathematical symbol "not equals to"? ... Right?.
The output, for not having the small circle, tells us that his true function output is high (1).
So:
When its inputs are not equal the output will be high (1)
Thus:
When its inputs are equal the output will be low (0).

But adding this gate occurs what I mention you in my post #8.
And more; If you study.

Sorry for so many words.

Let me assume that you already have your design as shown in Figure M 1
I would like you to change the LOGICSTATE by switches

Your design should include:
1: Control Panel.
2: Comparator
3: Attempts Counter
4: Logic Circuitry.

1: The Control Panel should contain:
All the 8 switches or LOGICSTATE.
The GUESS button.
The Reset button.
Some resistors and one capacitor.

2: The Comparator must contain:
Two Comparators cascaded.
8 signals from the Control Panel. But through 74LS253 which I recommend.
The control inputs of the first comparator connected as seen in Figure M 1.
Also come to the Comparator Circuit GUESS and Reset signals.

Here I am going to recommend the use of the 74LS253 which is an octal D-type Flip-Flip with its control inputs Clock & Reset.
What makes this device?
octal; has, inside, 8 Flip-Flop's type D, one for each switch.
On the positive transition of the pulse applied to the input clock, the state of its D's passing to their corresponding Q's
if its reset input control is false (1).
But if its reset input control is true (0)
All its Q's outputs change to zero (0).

3: Counter Attempts should contain:
The 4017 recommended by rabsf.

4: The Logic Circuitry must contain:
some logic gates, LED’s, resistors.
input signals: GUESS, A>B, A<B, A=B, 3 trials.
An output named Wrong

Pseudo Boolean formulas for this circuitry are:
Wrong if: (A<B OR A>B) AND GUESS.
LED green on if A=B
Red-Green LED flashes if 3 trials have passed.

Do you think you can continue with your project with all this talk?
Please: if something is not clear to you, let me know immediately.
I'll watch and try to explain better any misunderstanding.

 

Mr.Carlos,

I am so grateful for your detailed explanation. It was not long for me at all and every word was useful for me. I am still working on the circuit. If I had problem, I will certainly get back.

Thank you so very much...

 

Here I am going to recommend the use of the 74LS253 which is an octal D-type Flip-Flip with its control inputs Clock & Reset.
What makes this device?

Hi Mr Carlos,

74LS253 is a MUX. I think you meant to say 74LS273?

Allen

 

Hi absf

Yes sorry for the mistake.

my finger went to press another key

 

Hi absf

Yes sorry for the mistake.

my finger went to press another key

Please don't complains your fingers, the problem is in the brain, because the number 7 is not beside the 5, and this is not a big deal, we will do the the similar things.

 

Hello MrCarlos,

I have some questions that I hope you would forgive me asking them because they may seem quite simple. As I said I am very new to this subject.

So I strongly suggest you draw back your original design.
But as shown in Figure M 1.jpg.

I have enclosed M1 again. There's an item there which I could not find it in proteus. Please let me know the name.

From your post #6 You remove a comparator.
What is the reason ?.

I just wanted to reduce the 8-bit comparator to 4-bit comparator and I think one 7485 is enough for this work like the enclosed 4-bit comparator. Please kindly explain why I should have two comparators to compare two 4-bit numbers?

And add an exclusive OR gate whose inputs are connecting through few LED's.
The exclusive OR gate; I do not think that helps your design.

Please correct me if I am wrong. 4017 clock needs a pulse generator and the xor gate does not do it. I should transfer A>B and A<B to a pulse generator?

I would like you to change the LOGICSTATE by switches

2: The Comparator must contain:
Two Comparators cascaded.
8 signals from the Control Panel. But through 74LS273 which I recommend.
The control inputs of the first comparator connected as seen in Figure M 1.
Also come to the Comparator Circuit GUESS and Reset signals.

74LS273, I tried to find a simple circuit through with I could figure out its function but didn't really find anything. I will be thankful if you kindly link me to one.
Also, I tried to modify M1 circuit as enclosed. Please let me know where I am going wrong.(see M11 as enclosed)

Do you think you can continue with your project with all this talk?

I am very new to the subject. But I am trying. I hope you guys won't give up helping me.

Please: if something is not clear to you, let me know immediately.
I'll watch and try to explain better any misunderstanding.

Again, thanks so much.

 

Hello srysdn

You Asked --à My Answer.

0-0-0-0-0-0-0-0-0-0
The Item Name is THUMBSWITCH-HEX.
There are also THUMBSWITCH-DEC.

Is nothing more than a Digi-Switch.
The number on its face is the binary code on its terminals
You can locate in the DigiKey.com.
(A.jpg)

0-0-0-0-0-0-0-0-0-0
We could say that in this case: the largest is the better.
Trying to guess a single digit number is easier (0-15).
Instead two numbers would be more difficult to guess the key number (0-256)

The decision is yours, a single number or two.

0-0-0-0-0-0-0-0-0-0
You say:
Please correct me if I am wrong. 4017 clock needs a pulse generator and the xor gate does not do it. I should transfer A>B and A<B to a pulse generator?

Take it easy.

Yes, the 4017 needs a signal Clock for displacing on its outputs a high level (1).

Remember this paragraph?
Pseudo Boolean formulas for this circuitry are:
Wrong if: (A<B OR A>B) AND GUESS.
LED green on if A=B
Red-Green LED flashes if 3 trials have passed.

The signal named "Wrong" (generated in 4: Logic Circuitry) will be counted by the 4017.
"Wrong" is the clock signal for 4017.
By the way: You've done this part of your design ? (4: Logic Circuitry)

0-0-0-0-0-0-0-0-0-0
You say:
Also, I tried to modify M1 circuit as enclosed. Please let me know where I am going wrong.(see M11 as enclosed)

Very close, very close.
But take a look at my design "The Comparator.DSN"
enclosed in the ZIP file.

look at the connectors name.
Those who enter the left coming from the 1: Control Panel.
Those who depart from the right, arrive to the 4: Logic Circuitry.

0-0-0-0-0-0-0-0-0-0
A few extra words:
I repeat, your design should contain the following parts:
1: Control Panel.
2: Comparator
3: Attempts Counter
4: Logic Circuitry.

How many of these parts, we've already done?

 

Hello MrCarlos,

I am coming back with a circuit as enclosed that I know it does not show how much time I put on it.

1. The reset and the guess buttons in the control panel: The reset button triggers MR in flipflop 74LS273 to null the guess button that triggers the clock (Please correct me if it is wrong).
I will be grateful if you kindly guide how to connect them.

2. Regarding the pseudo boolian formula: I think the AND gate causes one of the LEDs in the counter always flash. When I do it on the paper it does not, but in proteus....

Please kindly let me know where I am wrong and I will try to correct it.

 

If any inputs of the CMOS gate open that it could causing the output oscillation, so the inputs should have a low or high level to settle down.

For any inputs of CMOS gate that the pull low or pull high resistor can be using 1K~47K.

For a TTL pull low that the resistor will be using as 330Ω, and the pull high resistor can be using as 330Ω~33K, If any inputs of the TTL gate open that it could treat it like as a high level.

Go to check the inputs as clk and MR and others to make sure they are on the right logical level.

If every inputs logical level are right then the rest problems are the connections and logic problems.

 

Hello sryzdn

Very, Very nice try.
I can see your design in the image that you enclose.
There are some things to improve.

It is almost equal to my design.
but. . . Imagine you have 2 buttons to reset the system ?
Now: there will always be a better way to draw a diagram.

I think there are already many messages back and forth, and also too long to achieve the goal.
In addition to this effort you make to achieve your goal. . .

You are very close to achieving your goal, just missing some minor details.
So without further ado, take a look at the design that I attached.

Analyze it well and tell me in your next post what was missing to improve your design.