It might be best to reset every thing, Can be done at power-up.

 

@djsfantasi I guess my main question with the OR gate, or I guess that specific OR gate, is what is the arrangement for the pins? It's still a little fuzzy for me.

Do you mean the pin assignments? The OR gate comes in a quad package. It's name is CD4001 CD4071. And it's pin assignments are shown below.

By the way, the pin assignments for the 4017B are shown below:

And just to be complete, the pin assignments for the 4049 are:

And good catch. Bernard and you are correct that the connections should be moved up one position. Sorry I missed that!


As far as the reset on my original circuit, I had the counter wired so that once one more pulse came in, it would return to the first (now empty) position. You could remove that connection and wire all the reset pins to one push button.

EDIT: Inserted the correct pinout. Thanks, Alec_T

 

I think you could eliminate the 4049 IC: just use the fourth gate of the 4071 IC in the clock-debounce part instead of the two 4049 gates.
BTW, the 4001 contains NOR gates; not OR gates (which would require a reconfiguration of the circuit).

 

Pinout is the same for 4001 & 40 71; would still recomend 74AC32 or second best 74HC32.
Might also free up reset by connecting count out 3 to clock enable; fourth SW pulse then would leave all LED's on untill reset.

 

So when I try to design the PCB, i cannot make it without having two paths cross (at least to my knowledge). Is there anyway to overcome this?

 

You may be able to route under an IC package or other component or just use a jumper.

 

Might also free up reset by connecting count out 3 to ckock enable; fourth SW pulse then would leave all LED's on untill reset.

I like this idea so much, I used it in an updated design. I'll attach it later. But don't you mean the third SW press? Counting presses:

1. O0 -> O1
2. O1 -> O2
3. O2 -> O3, and the clock should be disabled from further presses...

JoshS - Two points about your PCB design. Don't until you've breadboarded and tested the circuit. I didn't simulate my design, and I'm beginning to think there's an oddity in the debounce circuit. Secondly, wrt Alec_T's remarks: clipped component leads make excellent jumpers. Just be sure they clear the traces below.

 

I think you could eliminate the 4049 IC: just use the fourth gate of the 4071 IC in the clock-debounce part instead of the two 4049 gates.
BTW, the 4001 contains NOR gates; not OR gates (which would require a reconfiguration of the circuit).

Oops, I didn't mean the 4001 obviously. I meant the 4071, but as Bernard pointed out the pinouts are the same. I've edited the original post.

Interesting idea about using the extra gate. I searched for an example, but couldn't find one.

The oddity of my debounce circuit, that I mentioned, is that when the switch is not pressed, it's output is high. The LEDs would advance only when the pushbutton is pressed and THEN RELEASED. I'm also not sure what would happen on power up. This secondary concern may be irrelevant, as it probably is a good idea to reset on power on in any case as Bernard said. To fix the oddity, remove one inverter from the circuit.

Bernard - is the last OR gate necessary? Is it used to drive the LED or can it be omitted? If so, then one 4071 can be used for two circuits. Thus in the TS example, one PCB can be used for each "team".

JoshS - Where is this going to be used? It looks like a device that can be used in a classroom...

Sorry for the rambling nature of this post. It's kind of a brain dump...

 

Re # 27; In a around about way, I was trying to say 4th SW press is a do nothing.

 

Bernard - is the last OR gate necessary? Is it used to drive the LED or can it be omitted? If so, then one 4071 can be used for two circuits. Thus in the TS example, one PCB can be used for each "team"

I was wondering what you thought about this?

 

As this does not appear to br a high reliability requirement project I think it will be ok to use 3rd OR elsewhere else. I presume that LED current planed for about 15 mA? Would guess a 4017 output would drop to around 3V with a 15 mA load with Vcc of5 V, then the resistor would need to be lowered for # 3 LED-- then is output still a logic 1 ?? Test indicated?
For de-bounce, cannot come up with reliable ckt. with out an active componet, like a schmitt inverter. Tried 10K from Vcc to SW & 220k R, other end of 220k to schmitt input along with a .1 uF to gnd. Other side of SW to gnd. I tested with 74HC132 NAND as 40106 was faulty.

 

Hi

You could use a CD4015B Shift Register...it has latched outputs and reset.

eT

 

Good idea, I tried selling 74AC164 or 74HC164 with no luck .

 

SW bounce supressor for each section & automatic clear for all SR's including shift register 3 bit counter.
4071 high output V: Vcc 5.37 V; 2.1 mA = 4.42 V, 3 mA = 3.9 V, 4 mA = 3.24 V, 4.6 mA= 2.6 V = direct connection for LED; 4.9 mA = 2.2V red LED.

 

Hi

Here's a version with CD4015B.
The graphic only shows half the circuit but the other half works the same way.

eT

 

I think that you hit the nail square on the head, great ckt.
Nit picking time: Might add pin nos. for remainder of U3. C 6 might be a bit small if this resets 6 additional ckts.

 

Hi Bernard

Good suggestions. Here's an updated circuit. Reset pulse is about 7ms.

eT