Leakage in Supercapacitor Model

Discussion in 'The Projects Forum' started by jerryfan, Aug 12, 2015.

  1. jerryfan

    Thread Starter New Member

    Aug 12, 2015
    2
    0
    I'm working on testing a proposed model for supercapacitors. The researchers proposed a equivalent circuit for a supercapacitor cell. In their experiment, they charged the supercapacitor at 4A for 5s, then disconnected the source and let the cell sit for 4000s. Normally a capacitor will retain all the charge on each of its plates if the circuit is broken, but there is leakage in a supercapacitor. The proposed equivalent circuit is suppose to model this leakage.

    What I'm trying to do is test the model using LTspice. I've drawn the circuit but I'm wondering if my setup is correct because I'm not sure how to represent the removal of the current source. What I have tried is using PWL for the current; for the first 5s it outputs 4A then after 5s it forces 0A. Does setting the current source to 0A emulate physically disconnecting the circuit? Does the ground that LTspice forces on the circuit play a role during the 4000s?

    Thanks
     
  2. ronv

    AAC Fanatic!

    Nov 12, 2008
    3,283
    1,245
    I
    Looks good to me. No problem with the pwl or ground.
    Is the ESR correct for the fast capacitor?
    Need some ESL?
     
  3. jerryfan

    Thread Starter New Member

    Aug 12, 2015
    2
    0
    Thanks for the help but whats ESL? I'm not very familiar with circuits
     
  4. Alec_t

    AAC Fanatic!

    Sep 17, 2013
    5,791
    1,103
    Welcome to AAC!
    ESL = Equivalent Series Inductance.
     
Loading...