Hi.
Please help me solve the problem with my LDO in the picture below. Thank you.

 

Is this breadboard data or from a simulation?
From where comes Vbg?
What powers this op amp?
What MOSFET are you using?
My guess (and I am guesing) is the supply on the op amp is 3V and above that the op amp output cannot rise high enough to correctly drive the FET, so that pulls the output out of regulation.

 

Hi.

Is this breadboard data or from a simulation?

The figures above are not directly taken from simulation but it is very similar to my simulation results.
I simulated it in Cadence.

From where comes Vbg?

I used a designed bandgap circuit to provide Vbg. It is relatively good.

What powers this op amp?

Sorry, do you mean power consumption?
If so, it is about 30uW.
The open loop gain is about 60dB.

What MOSFET are you using?

I am using PMOS from TSMC0.18um.

My guess (and I am guesing) is the supply on the op amp is 3V and above that the op amp output cannot rise high enough to correctly drive the FET, so that pulls the output out of regulation.

I used Vin [2to 3.3V] to provide power supply for opamp.

 

Hello anhnha!
Any update on this? Have you figured out what parameter to change in order to shift the graph to your desired value?
Thanks!