LDO problem

Discussion in 'General Electronics Chat' started by anhnha, Apr 21, 2014.

  1. anhnha

    Thread Starter Active Member

    Apr 19, 2012
    773
    47
    Hi.
    Please help me solve the problem with my LDO in the picture below. Thank you.

    [​IMG]
     
    Last edited: Apr 21, 2014
  2. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,388
    1,605
    Is this breadboard data or from a simulation?
    From where comes Vbg?
    What powers this op amp?
    What MOSFET are you using?
    My guess (and I am guesing) is the supply on the op amp is 3V and above that the op amp output cannot rise high enough to correctly drive the FET, so that pulls the output out of regulation.
     
  3. anhnha

    Thread Starter Active Member

    Apr 19, 2012
    773
    47
    Hi.
    The figures above are not directly taken from simulation but it is very similar to my simulation results.
    I simulated it in Cadence.
    I used a designed bandgap circuit to provide Vbg. It is relatively good.
    Sorry, do you mean power consumption?
    If so, it is about 30uW.
    The open loop gain is about 60dB.
    I am using PMOS from TSMC0.18um.
    I used Vin [2to 3.3V] to provide power supply for opamp.
     
  4. rfenergyharvester

    New Member

    Apr 23, 2015
    10
    0
    Hello anhnha!
    Any update on this? Have you figured out what parameter to change in order to shift the graph to your desired value?
    Thanks!
     
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