It's getting hot because you're missing an Emitter resistor, as that's an Emitter Follower which can't provide you with voltage gain, only current gain but I see no need for the Darlington NPNs anyway. The FET doesn't need any drive current to drive the Gate, it only needs sufficient voltage @ a few uA, and that small current is only flowing in the Gate resistor. What FET model are you using so I can check the data sheet on it? If the 5V from the Pic is not high enough then we can use those 2 NPNs in a Common Collector configuration. That is if they haven't been smoked yet.

 

If you're using the IRF510 you can use two NPN voltage drivers like this to bring up your Gate voltage. This will insure that the FET is completely turned on.

 

Gibby, I just realized that I had regressed into a none Microcontroller mindset when I posted that last schematic. You need only one NPN to drive the gate of the FET. To do this you need only invert your logic in code. Do you understand what I mean?

 

Hi,
I have similiar problem with my laching circuit.I tried it too hard to find proper way for completion.Your circuit design need improvisation according to your piezo switch.By the way search about it more on the net.

 

I'm reposting this because the one I posted last night vanished? Looking back over this schematic you posted I noticed R1, R2 & R4. What are they for? You should also put ~ 10uF on the output of the Reg to GND.

Here's an updated schematic using only one NPN voltage amplifier to drive the gate of the FET. Of course you do need to modify your code to use it.

 

Final solution was to have no transistor from the picaxe to trigger the 510 mosfet. I put a 12k from the picaxe straight to the gate and 1M from gate to ground.

R1 and R2 are specs from the pic manufacturer and I replaced them with a 32k. R4 was just another spec from the manf. for limiting the current through a switch.

So far everything is working great.
Thanks

 

Glad to hear that it's working for you. Btw, the reason that I used one NPN driver ( in the last schematic ) was because I wanted to insure that the Vgs would be sufficient to completely saturate the FET. The spec sheet said Vgs = 2V min to 4V max. It's probably OK but what's your Vds when the FET is on?.... Just curious.