I have a latch with NOT gates as in the picture.
Let's assume that initially, switch is connected to Vcc then I have:
Input of upper NOT is 1 (logic)
Output of lower NOT is 1
Now if I look at the upper NOT:
Because its input is 1 => its output Q = 0
Next consider the lower NOT:
I am confused about the two possibilities bellow. Which one is right?
1)
Because input of the lower NOT is Q = 0 (result from upper NOT)
=> its output \(\overline {Q}\) = 1
2)
Because output of lower NOT \(\overline {Q}\) = 1 => its input has to be 0.
I mean that it is output of the lower NOT that cause its input to be 0.
I think #2 is maybe wrong because the input of NOT isn't affected by its output but not sure.
Let's assume that initially, switch is connected to Vcc then I have:
Input of upper NOT is 1 (logic)
Output of lower NOT is 1
Now if I look at the upper NOT:
Because its input is 1 => its output Q = 0
Next consider the lower NOT:
I am confused about the two possibilities bellow. Which one is right?
1)
Because input of the lower NOT is Q = 0 (result from upper NOT)
=> its output \(\overline {Q}\) = 1
2)
Because output of lower NOT \(\overline {Q}\) = 1 => its input has to be 0.
I mean that it is output of the lower NOT that cause its input to be 0.
I think #2 is maybe wrong because the input of NOT isn't affected by its output but not sure.
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