keeping count

Discussion in 'Homework Help' started by jerry928, Dec 9, 2014.

  1. jerry928

    Thread Starter New Member

    Dec 9, 2014
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    Hi, I'm using an Altera DE2 boats. I'm creating a counter that counts the number of times a user pushes a button. I'm using 74163 counter since I need to count 0-9 and I think it's easier to control. I must have it running on an internal clock. However, my counter didn't seem to be working to perfectly. when the button is pressed, P and T are true and the counter starts counting but it counts from 0-9 changing on the edge of clock. How am I able to implement this? how can I keep the single ou out count after the button is pressed and held even if the clock is 'clockkng'?
     
  2. MrChips

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    Oct 2, 2009
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    You don't need a continuous clock to trigger the counter. A simple push-button with debounce circuitry will do the job.
    If you must have the push-button action synchronized with a clock pulse, you can use a D-type flip-flop to register the push-button being pressed and then clock counter and clear the flip-flop.
     
  3. Shagas

    Active Member

    May 13, 2013
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    You don't need a clock . Your user push button IS the clock in this case. I'm assuming you are using some 74163 library in Quartus or something and running it on the DE2. You can figure out what combination of the output pins gives you a
    '9' value and you can make a 3 or 4 input and gate which will be connected to CLR.
    The DE2 buttons are equipped with switch debounce circuitry.
     
  4. jerry928

    Thread Starter New Member

    Dec 9, 2014
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    HI Shagas, thanks for the reply. So this is how I was thinking of doing it and this is how I had it: my push button was my clock. However one of the requirements for this was that we use the internal clock of the board to drive the clock of the counter, so using the push button as my clock isn't an option.
     
  5. WBahn

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    Mar 31, 2012
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    You should basically NEVER use random logic to clock circuitry in an FPGA (I'm assuming you are using an FPGA development board). The reason is that random logic is implemented using look-up tables and are inherently glitchy; it is even possible for signals to glitch when unrelated signals change state because the configurations are stored in the same SRAM cells.

    What you need is a state machine that goes from the IDLE state to the a COUNT state and then immediately to a WAIT state where it is waiting for the button to be released before it returns to the IDLE state. That's assuming your switches are debounced. If they aren't, then you can incorporate the debounce process into your state machine.
     
  6. jerry928

    Thread Starter New Member

    Dec 9, 2014
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    How would this look like? I just started learning about FSMs and I'm still having a hard time understanding the concept. I am using a FPGA board. Would you mind elaborating a bit more about how I should construct a state on the board?
     
  7. Papabravo

    Expert

    Feb 24, 2006
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    The state of a FSM is tracked by a register made up of flip-flops. The number of flip-flops in the state register is sufficient to represent all of the possible states. For example 3 flip-flops can represent 8 possible states. On each active edged of the clock the FSM will examine the present inputs and the present state and compute two functions:
    1. A next state function, which is then loaded into the state register
    2. An output function
    A potential simplifications is to make the output a function of the present state only.

    That's it in a nutshell. Questions?
     
  8. jerry928

    Thread Starter New Member

    Dec 9, 2014
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    I have a lot but I'm getting the idea. So it isn't necessarily wrong that I used the 163 counter. I just have to add a DFF in order to keep that value and thus making it a State in the FSM?
     
  9. WBahn

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    Mar 31, 2012
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    You can use the '163 if you want. Your state machine would simply control the inputs to the counter.

    Consider that your counter has a free-running clock, that means that when you increment the counter you need to apply the correct inputs for just ONE clock cycle, otherwise it will keep on incrementing.

    So think about the things that have to happen starting from just before someone presses the button until just after they release it, assuming that the button is held down for an arbitrarily long number of clock cycles (and also that it is held down for at least one clock cycle). At least at first, you can assume that the buttons are debounced.
     
  10. Papabravo

    Expert

    Feb 24, 2006
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    The'163 counter already has four flip-flops inside of it. It has a synchronous RESET, parallel LOAD, and enable inputs. On every clock edge you have a number of options:
    1. Increment the present count(state) by 1
    2. Hold the present count(state)
    3. Load a new count(state) from the four inputs
    4. Reset the count(state) to all zeros.
    It has everything you need for an FSM of up to 16 states. Can you work out what the values of the control inputs would be for each of those actions and put that information in a tabular form?
     
  11. WBahn

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    Mar 31, 2012
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    I've got to disagree about it having everything you need for an FSM up to 16 states. For instance, what if you need to go from State 7 to State 8 under one set of conditions and to State 3 under another set and to State 6 under yet another set?

    But even if it did, he needs far more than 16 states since he needs to maintain a count value ranging from 0 through 9 and then, for each on of those, needs to know if a button has just been pressed, a button has already been pressed and is still being held down, and a button has been released. Needs far more that than if the button also needs to be debounced.
     
  12. Papabravo

    Expert

    Feb 24, 2006
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    The answer to your question is that:
    1. You use increment to go from 7 --> 8
    2. You use Parallel Load to go from 7 --> 3
    3. You use Parallel Load to go from 7 --> 6
    If he needs one device to count from 0 to 9, then he can use a second device to implement the his FSM, or he can use discrete flip-flops, or shift registers or a Johnson counter. There is lots of room for creativity. I do agree that using MSI chips there is a huge premium on making sure the combinatorial logic for next state and output does not get out of hand. If it does a ROM is usually employed to reduce the chip count. I used to design this stuff all the time, but not so much anymore.
     
    Last edited: Dec 10, 2014
  13. WBahn

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    Okay, then how do you establish the value on the parallel load using only the '163 (since the claim is that it has everything that is needed)?

    I agree that for FSM's that are dominated by things that advance or retreat one state at a time that using a counter for the state registers can significantly reduce the glue logic needed for the transition logic, but I would argue that it almost never eliminates the need for additional logic to implement the FSM.
     
  14. Papabravo

    Expert

    Feb 24, 2006
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    Let me rephrase my earlier statement. It has everything you need to implement the state register portion of the FSM. As you have pointed out it lacks the combinatorial circuitry required to compute the next state and output functions that I alluded to in a previous post.
     
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