Post an image of your modulo 10 counter so we can talk over it.
If you examine it, you will see some logical gates placed in a way that they produce a '0' everytime 10 is reached on the count. That zero should be fed on the reset pin.
Of course this is what usually happens. Post your picture and we 'll talk more.
I'm afraid I don't understand what your circuit does. How is the AND circuit supposed to see the number 10? How is it supposed to reset the counter if it sets only the two middle FFs?
Notice that the designer has a AND gate that detects a 'HIGH' on the bits 0 and 2, which is basically when 5 comes up. Then he resets with the AND gate all of the FFs of the counter.
If you understood what he did, care to make another effort?
hello!! first we know that we require 12 modulo counter so so we require four bits and four flip-flops. Now check the attachment that i am providing....