JK Flip Flops

Discussion in 'General Electronics Chat' started by vrit_sunshine, Sep 24, 2007.

  1. vrit_sunshine

    Thread Starter New Member

    Sep 24, 2007
    1
    0
    if we set j=1,k=0 in a positively triggered jk flipflop then what is the output?
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    I have moved your post to its own subject. Please do not hijack another post - start your own.

    The truth table for a 74LS73 indicates the flip-flop will be set, assuming the reset input is high as well. The device's data sheet always gives that information.
     
  3. techroomt

    Senior Member

    May 19, 2004
    198
    1
    if an async input is active, it will follow that control, if not, it will be at its previously driven state. if a valid clock has occurred, then set.
     
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