The top op amp is a Summing Amplifier.Hello Codfail
Assuming that the Q's of Flip-Flops in the RESET state is 0 (zero volts).
No current flows through any resistor R.
Thus the output of operational amplifier located at the top, will be zero volts.
I don't get it that the LED will continue ON forever, when Vref is negative.Hi all
Well if this is the case:
The original question was:
Neglecting propagation delay, how long after the first clock pulse will the LED goes off.
The answer might be:
The LED will continue on forever.
No matter that we have changed the polarity of Vref.
Attached are some pictures to clarify this even be more.
But what the originator of this topic says?
If Vref is positive, the the difference V+ - V- is always positive, the output of the comparator is positive and the LED is never ON.I can not figure out how you guys got Vref to be negative 6 volts.
Ah! Thank you. I did not notice that +12 was switched to -12 volts.Hello shteii01
If you take a careful look at the attached pictures sure find out.
Remember that all measurements are with respect to ground.
Is there a source for this question and an associated errata sheet correcting the schematic diagram?The schematics is wrong.
Vref should be negative ( -6V )
I'm not sure if the schematic was corrected, i found this question while going through some pass papers for the course.Is there a source for this question and an associated errata sheet correcting the schematic diagram?
We can not "assume" the schematic is incorrect as the comparator has both -12V and 12V indicated on the comparator.
As drawn, the LED never energizes.
Has the professor given instructions to fix any and all "bad" schematics to ensure the wording of the problem statement over rules the associated diagrams? In the forums, I feel it's proper to "fix" any bad schematic to match the words of the problem, but I don't know how their professor feels about it.
So we are left with it's being a trick question with you explaining why it won't work as drawn, or the professor needs to exercise some due diligence when producing diagrams.I'm not sure if the schematic was corrected, i found this question while going through some pass papers for the course.
by Aaron Carman
by Duane Benson
by Duane Benson
by Duane Benson