JK Flip flop timing

Discussion in 'Homework Help' started by thexy, Jan 12, 2016.

  1. thexy

    Thread Starter Member

    Dec 13, 2015
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    I got synchronous up/down counter and parameters:
    Delay Time negation Tdelay.not,
    Delay Time and, or Tdelay.andor,
    Delay Time JK Flip flop Tdelay.ff
    Preparation time JK Flip Flop Tsetup.ff,
    Halftime Thold.ff=0
    What parameters are relevant for:
    a) Maximal frequenc on Takt T
    a) Minimal preparation time
    vvv.PNG
     
    Last edited: Jan 12, 2016
  2. WBahn

    Moderator

    Mar 31, 2012
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    You might try starting by defining what you mean by the different parameters. In particular, what is Takt T? What is Halftime Thold.ff? What is preparation time? If, as your thread title suggests, you are asking something about JK flip flops, then how would parameters for negation, and, and andor, come into play. If you asking something about a circuit that uses JK flip flops and these other gates, then how do you expect someone to provide any meaningful answer without a schematic of the circuit in question?
     
  3. thexy

    Thread Starter Member

    Dec 13, 2015
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    I'm sorry, I forgot to put photo. Here you go :)
     
  4. GopherT

    AAC Fanatic!

    Nov 23, 2012
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    That didn't help explain anything (at least for me).
     
  5. thexy

    Thread Starter Member

    Dec 13, 2015
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    I really don't know to explain more (how to translate this example, orginaly it's not on english)
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    So walk through the circuit and, relative to the rising edge of the clock, determine how long it will take for the signal to get to each node from A0 to A1. Then determine what the soonest the next rising edge of the clock can occur.
     
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