The clock signal has it's first rising edge (a transition from LOW to HIGH), at the beginning of period #5
- When the clock signal (CLK) is HIGH, the output Q cannot change.
- When the clock signal (CLK) is LOW, the output Q cannot change.
- When the clock signal (CLK) has a falling edge (a transition from HIGH to LOW), the output Q cannot change.
Therefore Q must be unknown in periods #1, #2, #3, and #4 because it was unknown in time period #1, and it has not changed.
Just before the rising edge at the beginning of time period #5, J=K=1 which means that when the rising clock edge arrives the flip-flop will do what?
Choose one of the following:
If your answer is 1 or 2 then you know the value of Q. If your answer is 3 or 4, then you still don't know and you must proceed to the next step. which time period has the next rising edge of the clock (CLK)?
- Clear to 0
- Set to 1
- Do nothing
- Toggle
but why is Q in 1 unknown?See post #14 in this thread. The values of J and K just before the rising clock edge determine the value of Q according to the state machine that you analyzed in your previous thread on the JK state machine. I wrote out the behavioral description of what happens when J and K assume certain values. Go back to that previous thread
http://forum.allaboutcircuits.com/threads/jk-flip-flops.118483/page-2
reread what I wrote in post #26, and this time pay attention so I don't have to keep repeating myself.