# Jitter in PLL

Discussion in 'General Electronics Chat' started by lkgan, Dec 31, 2009.

1. ### lkgan Thread Starter Member

Dec 18, 2009
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Hi everyone,

As shown in figure, a strictly periodic waveform, x1(t), contains zero crossings that are evenly spaced in time. Now consider the nearly periodic signal x2(t), whose period experiences small changes, deviating the zero crossings from their ideal points, which is suffering from jitter. (Plotting the total phase, δtotal, and the excess phase, δexcess, of the two waveforms, we observe that jitter manifests itself as variation of the access phase with time). Can anyone please explain to me what the bracket sentence means? And what is the meaning and difference of total phase and excess phase? How do calculate and plot the total and excess? Appreciate if anyone could answer my questions, thanks....

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Apr 5, 2008
15,806
2,390
Hello,

Did you have a search on the internet?
I found the three attached PDF's.

Greetings,
Bertus

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3. ### lkgan Thread Starter Member

Dec 18, 2009
117
0
Hi,

I have search in the internet, but can't find the explanation about the excess phase. Which pdf file given by you that explain about it? I can't really relate what you have given.

Apr 5, 2008
15,806
2,390
Hello,

Here I have two documents selected for the excess jitter.
Sorry, for the not so selective search at the first time.

Greetings,
Bertus

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5. ### lkgan Thread Starter Member

Dec 18, 2009
117
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Hi,

I still can't relate the link given by you and my questions. Can anyone relate it or know the answer in a simpler way?

6. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
783
In the case of total phase, as time advances the individual signals "advance" 360° with each successive cycle. If you take this phase as cumulative over time you get a linearly rising value of total phase for the reference waveform - since it is strictly periodic. Being part of the phase locked system, the phase locked signal advances on average by the same amount but there are instantaneous differences in the accumulated phase advance. These instantaneous differences in the phase locked signal are seen as deviations about the constantly rising total phase graph.

If you subtract the linearly increasing accumulated phase "advance" of the strictly periodic signal from the phase locked signal's accumulated phase you obtain the excess phase at any instant. It has both positive and negative deviations but on average is zero.

This seems a rather rather convoluted way of saying that the instantaneous phase changes of the locked signal can never be a perfect instantaneous copy of the the reference signal but when averaged over a sufficient time interval the phase changes are the same or are "in step".

7. ### lkgan Thread Starter Member

Dec 18, 2009
117
0
Hi t n k,

Thank you so much for your explanations, I finally understand what you have mentioned.

8. ### KL7AJ AAC Fanatic!

Nov 4, 2008
2,047
295
Let me attack this from a more pragmatic angle. The way to get a PLL to work without excessive jitter is to have the most STABLE VCO possible. Unfortunately, PLL technology allows you to have a really lousy VCO, yet still stay locked on frequency. A lot of modern PLL designs use cheap silicon as a substitute for sound design. A good VCO will remain ALMOST on frequency without a feedback loop. This is expensive to do, but most importantly requires excellent ANALOG (r.f.) design skills, which are almost non existent in so much commercial equipment.

Eric

9. ### Ron H AAC Fanatic!

Apr 14, 2005
7,050
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In addition, some phase detectors have a dead band which causes the loop to hunt back and forth across the dead band. The loop can be biased to one side of the band, but then the bias will cause integrator droop, which will also cause jitter.
Also, some phase detectors (e.g. XOR) have inherent phase ripple.

10. ### Ron H AAC Fanatic!

Apr 14, 2005
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Also RC VCOs are inherently noisier than LC VCOs. With LC VCOs, noise is generally inversely proportional to circuit Q.
At least, this is what I remember from my old PLL design days (15-20 years ago).

11. ### lkgan Thread Starter Member

Dec 18, 2009
117
0

Hi, can you please explain more about what's dead band in PLL? Is hysterisis what you meant? And what is it the integrator droop about? Can please eleborate more, I am interested to know. Thanks....

12. ### Ron H AAC Fanatic!

Apr 14, 2005
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Well, as I said in my second post, it's been many years, but I seem to remember that the CD4046 phase comparator II has such a dead band. See this Wikipedia article,and search for dead band.
In the 4046, the phase detector drives a bang-bang charge pump. The capacitor in the loop filter serves as the integrator. A resistor in parallel with the capacitor will bias the detector to one side of the dead band, but between phase sample updates, the VCO control voltage (the voltage across the capacitor) will drift toward ground, causing phase jitter.