JFET source follower design

Discussion in 'Homework Help' started by rushinge, Jun 13, 2010.

  1. rushinge

    Thread Starter New Member

    Jun 13, 2010
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    I'm in the middle of an extremely complicated (and difficult) project but in this stage I need help with a relatively simple concept. I have designed a sample-and-hold circuit and a comparator circuit but I need a buffer in-between the two to prevent the comparator from drawing too much current from the sample-and-hold.

    If you'll look at the attachment you can see I'm using a matched pair of two n-channel JFETs (model to be determined). The top is a source follower and I'm using the bottom as an active load for the follower. I'm trying to get the output voltage to equal the input voltage (or be very close).

    If I'm understanding correctly then the current through the bottom JFET must be equal to the current through the top JFET. To that end I'm thinking that the resistance presented to the source of J1 by R12, R4 and R5 and maybe the input resistance of Q6 must be equivalent to the resistance at the source of J2 which is simply R13. However I'm not really sure how to calculate what's the resistance at the source of J1.

    Am I using the right approach here? If so how can I calculate the resistance presented to the source of J1?
     
  2. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    You shouldn't need R4 and R5.
    The impedance at the lower end of R12 is (R12+1/gm), where gm is the transconductance of the JFET. I don't think this answers your question, but I don't really understand it.
    I used a similar circuit for a similar application over 30 years ago, although it had some enhancements. I used this technique because I needed a high speed, low offset voltage, low bias current voltage follower. Today I would use a high speed op amp. Why aren't you using one? Does your homework require that you use this matched JFET technique?
     
  3. rushinge

    Thread Starter New Member

    Jun 13, 2010
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    My homework is to design an build a complete ADC (of the successive approximation type) using all discrete components. Forbidding the use of op-amps was the main purpose of this rule. (What can I say, they like to make it difficult.) R4 and R5 are there to DC bias Q6 at 1/2 Vdd (15V). Q6 is one of the inputs to my comparator.

    If you refer to my attached simulation results (Which I'll try attaching to my original post since the attachment "manage attachments" window isn't loading now) you can see the problem I'm currently trying to solve. The output of the follower (In Blue) is "weaker" than the input signal and doesn't get driven as far towards the rails as the input signal is. I think this is because Q6 is drawing too much current due to mismatched impedances on the J1 and J2 sources. Or maybe I'm just looking at it the wrong way. I've got to find a way to fix it so that the source follower output follows the input closely.
     
  4. rushinge

    Thread Starter New Member

    Jun 13, 2010
    3
    0
    My homework is to design an build a complete ADC (of the successive approximation type) using all discrete components. Forbidding the use of op-amps was the main purpose of this rule. (What can I say, they like to make it difficult.) R4 and R5 are there to DC bias Q6 at 1/2 Vdd (15V). Q6 is one of the inputs to my comparator.

    If you refer to my attached simulation results you can see the problem I'm currently trying to solve. The output of the follower (In Blue) is "weaker" than the input signal and doesn't get driven as far towards the rails as the input signal is. I think this is because Q6 is drawing too much current due to mismatched impedances on the J1 and J2 sources. Or maybe I'm just looking at it the wrong way. I've got to find a way to fix it so that the source follower output follows the input closely.
     
  5. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Get rid of R4 and R5. They are the source of your problem. The JFET source follower provides the bias.
     
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